公开(公告)号：US20220344285A1

公开(公告)日：2022-10-27

申请号：US17720435

申请日：2022-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junsu JEON ,  Subin Kim ,  Byungmoo Kim

IPC: H01L23/60 ,  H01L23/00 ,  H01L23/58

Abstract: A semiconductor device includes a semiconductor substrate including a main chip region, a guard ring surrounding the main chip region, a moisture-proof ring surrounding the guard ring, an electrode structure in contact with the semiconductor substrate in the main chip region, and at least one metal pattern structure extending from the electrode structure to the moisture-proof ring. The at least one metal pattern structure is a connection line that grounds the moisture-proof ring.

公开(公告)号：US20240055427A1

公开(公告)日：2024-02-15

申请号：US18143187

申请日：2023-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin KIM ,  Namjae Kim ,  Subin Kim ,  Byungmoo Kim ,  Joongwon Jeon

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L21/823475 ,  H01L23/528 ,  H01L21/823493 ,  H01L2029/7858

Abstract: A semiconductor device including: a substrate including a PMOS region, an N-well tap forming region, and a boundary region; PMOS field effect transistors on the PMOS region; an N-well tap region doped with N-type impurities in the N-well tap forming region; a first metal pattern connected to at least one impurity region of the PMOS field effect transistors, wherein the first metal pattern extends so that an end of the first metal pattern is positioned on the boundary region; a second metal pattern electrically connected to the N-well tap region, wherein the second metal pattern extends so that an end of the second metal pattern is positioned on the boundary region; a first contact plug on the first metal pattern; a second contact plug on the second metal pattern; and an upper wiring on the first and second contact plugs.

公开(公告)号：US11314915B2

公开(公告)日：2022-04-26

申请号：US16859323

申请日：2020-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Kim ,  Byungmoo Kim ,  Jaehwan Kim ,  Junsu Jeon

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/398

Abstract: A method of designing a layout of a semiconductor device includes determining from among a plurality of integrated circuit (IC) blocks in the semiconductor device a selection IC block for which a layout is to be changed, changing an spacing interval at which fin structures included in the selection IC block are spaced apart from each other in a first direction from a first spacing interval to a second spacing interval, and determining in the selection IC block locations of source/drain regions connected to the fin structures spaced apart from each other in the first direction at the second spacing interval.