公开(公告)号：US20240266269A1

公开(公告)日：2024-08-08

申请号：US18626388

申请日：2024-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： GYUJIN CHOI ,  JAE-EAN LEE ,  CHANGEUN JOO

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/08 ,  H01L25/105 ,  H01L2224/0603 ,  H01L2224/08235

Abstract: Disclosed is a semiconductor package device comprising a semiconductor chip including first and second chip pads on an active surface of the semiconductor chip, and a redistribution substrate on the first and second chip pads. The redistribution substrate includes first and second redistribution patterns sequentially stacked on the active surface. The first redistribution pattern includes a first via part and a first via pad part vertically overlapping the first via part. The second redistribution pattern includes a second via part and a second via pad part vertically overlapping the second via part. The first via part contacts the first chip pad. The second via part contacts the second chip pad. A length of the second via part is greater than that of the first via part.

公开(公告)号：US20230187380A1

公开(公告)日：2023-06-15

申请号：US18064241

申请日：2022-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGEUN JOO ,  EUNKYOUNG CHOI ,  OHGUK KWON

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/29 ,  H01L23/481 ,  H01L23/3157 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/26125

Abstract: A semiconductor package includes a first semiconductor chip having a first surface and a second surface. First connection pads are adjacent to the first surface. A second semiconductor chip has a lower surface facing the first surface of the first semiconductor chip and includes second connection pads, Connection bumps contact the first connection pads and the second connection pads between the first semiconductor chip and the second semiconductor chip. An adhesive layer is interposed between the first semiconductor chip and the second semiconductor chip to at least partially surround the connection bumps. The adhesive layer includes a protruding portion protruding from a side surface of the second semiconductor chip. A barrier structure covers a portion of the first connection pads, partially overlapping the second semiconductor chip on the first surface, and contacting the protruding portion of the adhesive layer.

公开(公告)号：US20210143118A1

公开(公告)日：2021-05-13

申请号：US16947093

申请日：2020-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHANGEUN JOO ,  GYUJIN CHOI

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31

Abstract: A semiconductor package includes a lower redistribution layer including an insulating pattern having an opening and a via in the opening; a first semiconductor chip including a chip pad, a passivation layer, and a pad bump connected to the chip pad; and a first encapsulant on the lower redistribution layer and the first semiconductor chip. The opening defines a lower surface and a side surface of the pad bump, and the via is in physical contact with the lower surface and the side surface of the pad bump.