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    SEMICONDUCTOR DIE, SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DIE, SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210066145A1

    公开(公告)日：2021-03-04

    申请号：US17006186

    申请日：2020-08-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： TAEHYO KIM ,  CHANHO KIM ,  DAESEOK BYEON

    IPC: H01L21/66 ,  H01L23/00 ,  H01L27/11573

    Abstract: A nonvolatile memory device includes a memory cell region including first pads and a peripheral circuit region including second pads. The regions comprises switches that are electrically connected with the pads, respectively, a test signal generator that generates test signals and to transmit the test signals to the switches, internal circuits that receive first signals through the pads and the switches, to perform operations based on the first signals, and to output second signals through the switches and the pads based on a result of the operations, and a switch controller that controls the switches so that the pads communicate with the test signal generator during a test operation and that the pads communicate with the internal circuits after a completion of the test operation. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

    NON-VOLATILE MEMORY DEVICE
    5.
    发明申请
    NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20210065799A1

    公开(公告)日：2021-03-04

    申请号：US16944312

    申请日：2020-07-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： CHANHO KIM ,  KYUNGHWA YUN ,  DAESEOK BYEON

    IPC: G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10

    Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region. The memory cell region includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210066282A1

    公开(公告)日：2021-03-04

    申请号：US17002149

    申请日：2020-08-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： CHANHO KIM ,  JOO-YONG PARK ,  DAESEOK BYEON

    IPC: H01L25/18 ,  H01L23/00

    Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.

    NON-VOLATILE MEMORY DEVICE
    7.
    发明申请
    NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20210066278A1

    公开(公告)日：2021-03-04

    申请号：US16863736

    申请日：2020-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： CHANHO KIM ,  KYUNGHWA YUN ,  DAESEOK BYEON

    IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00

    Abstract: A non-volatile memory device includes a first semiconductor layer having a stair area and a cell area having a memory cell array formed therein, and a second semiconductor layer including a page buffer connected to the memory cell array. The first semiconductor layer includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210066277A1

    公开(公告)日：2021-03-04

    申请号：US16850493

    申请日：2020-04-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： CHANHO KIM ,  JOO-YONG PARK ,  DAESEOK BYEON

    IPC: H01L25/18 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11582 ,  H01L49/02 ,  H01L27/11565 ,  H01L23/00 ,  H01L27/11575

    Abstract: A three-dimensional semiconductor memory device, including a first chip and a second chip stacked on the first chip may be provided. The first chip may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, and second contact plugs, and a passive device on and electrically connected to the second contact plugs. The second chip may include a second substrate including a cell array region and a contact region, which vertically overlap the second peripheral circuit region and the first peripheral circuit region of the first chip, respectively. The second chip may further include gate electrodes, and cell contact plugs disposed on the contact region of the second substrate and on end portions of the gate electrodes. The first passive device may be vertically between the gate electrodes and the second contact plugs and may include a first contact line.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220139897A1

    公开(公告)日：2022-05-05

    申请号：US17577647

    申请日：2022-01-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： CHANHO KIM ,  JOO-YONG PARK ,  DAESEOK BYEON

    IPC: H01L25/18 ,  H01L23/00

    Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.

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