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    MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT
    1.
    发明申请
    MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT 有权

    公开(公告)号：US20220122673A1

    公开(公告)日：2022-04-21

    申请号：US17227501

    申请日：2021-04-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SEUNGYEON KIM ,  DAESEOK BYEON ,  PANSUK KWAK ,  HONGSOO JEON

    IPC: G11C16/24 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  G11C16/26

    Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

    MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT
    2.
    发明申请
    MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT 有权

    公开(公告)号：US20220406385A1

    公开(公告)日：2022-12-22

    申请号：US17898885

    申请日：2022-08-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SEUNGYEON KIM ,  DAESEOK BYEON ,  PANSUK KWAK ,  HONGSOO JEON

    IPC: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210005629A1

    公开(公告)日：2021-01-07

    申请号：US17025479

    申请日：2020-09-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： BONGSOON LIM ,  SANG-WAN NAM ,  SANG-WON PARK ,  SANG-WON SHIM ,  HONGSOO JEON ,  YONGHYUK CHOI

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11573 ,  H01L23/522 ,  G11C7/18 ,  H01L27/11519 ,  H01L27/11526 ,  G11C8/14

    Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM THEREWITH
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM THEREWITH 有权

    公开(公告)号：US20230115503A1

    公开(公告)日：2023-04-13

    申请号：US17836831

    申请日：2022-06-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SUJEONG KIM ,  BONGSOON LIM ,  HONGSOO JEON

    IPC: H01L27/11575 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11582

    Abstract: A semiconductor device may include stacks extended in a first direction on a substrate, separation structures extended in the first direction and respectively provided between the stacks, vertical channels penetrating each of the stacks, bit lines extended in a second direction crossing the first direction, each of the vertical channels being overlapped with a pair of the bit lines, and contact plugs connecting the bit lines to the vertical channels. Each of the stacks may include electrodes stacked on the substrate and at least two upper separation patterns dividing an upper one of the electrodes into several portions in the second direction. The vertical channels may be classified into a plurality of types, depending on a distance from one of the separation structures in the second direction, and each of the bit lines may be connected to all types of the vertical channels.

    INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM INCLUDING SAME
    6.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM INCLUDING SAME 有权

    公开(公告)号：US20220181284A1

    公开(公告)日：2022-06-09

    申请号：US17513132

    申请日：2021-10-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HOMOON SHIN ,  JOOYONG PARK ,  HONGSOO JEON ,  PANSUK KWAK

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

    Abstract: An integrated circuit device includes; a peripheral circuit structure including a peripheral circuit, a first insulating layer covering the peripheral circuit, extension lines in the first insulating layer, and a first bonding pad in the first insulating layer, and a cell array structure including a conductive plate, a memory cell array below the conductive plate, a second insulating layer covering the memory cell array, a second bonding pad in the second insulating layer, a conductive via on the conductive plate, and a line connected to the conductive via. The first bonding pad contacts the second bonding pad, and the integrated circuit device further includes contact plugs electrically connecting the line to the extension lines.

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