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公开(公告)号:US20210005629A1
公开(公告)日:2021-01-07
申请号:US17025479
申请日:2020-09-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: BONGSOON LIM , SANG-WAN NAM , SANG-WON PARK , SANG-WON SHIM , HONGSOO JEON , YONGHYUK CHOI
IPC: H01L27/11582 , H01L27/11565 , H01L27/11556 , H01L27/11573 , H01L23/522 , G11C7/18 , H01L27/11519 , H01L27/11526 , G11C8/14
Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.
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公开(公告)号:US20220020434A1
公开(公告)日:2022-01-20
申请号:US17489988
申请日:2021-09-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: YONGHYUK CHOI , JAE-DUK YU , KANG-BIN LEE , SANG-WON SHIM , BONGSOON LIM
IPC: G11C16/10 , G11C16/08 , G11C16/34 , H01L25/065 , H01L25/18 , H01L23/00 , G11C16/04 , H01L27/11582 , H01L27/11556
Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.
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公开(公告)号:US20210043244A1
公开(公告)日:2021-02-11
申请号:US16810527
申请日:2020-03-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: YONGHYUK CHOI , BONGSOON LIM , JAEDUK YU
IPC: G11C11/408 , G11C11/4094 , G11C16/04 , G11C16/10 , G11C16/26 , G11C5/02
Abstract: A memory device includes word lines stacked on an upper surface of a substrate, channel structures penetrating through the word lines, and each including channel regions connected to one another in a first direction perpendicular to the upper surface of the substrate, and word-line cuts extending in the first direction and dividing the word lines to blocks. The word lines and the channel structures provide memory cell strings, and each of the memory cell strings include memory cells arranged in the first direction. The memory cells included in at least one of the memory cell strings include a first memory cell and a second memory cell disposed at different positions in the first direction, and the number of bits of data stored in the first memory cell is less than the number of bits of data stored in the second memory cell.
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公开(公告)号:US20190371408A1
公开(公告)日:2019-12-05
申请号:US16199098
申请日:2018-11-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: CHANGYEON YU , MINSU KIM , HYUN-WOOK PARK , BONGSOON LIM
Abstract: A memory device includes a cell array and a page buffer circuit. The cell array includes first and second cell strings respectively connected to first and second bit lines. The page buffer circuit is configured to apply an erase voltage to the first bit line and to allow the second bit line to be in a floating state, when an erase operation is performed on memory cells of the first and second cell strings.
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公开(公告)号:US20230115503A1
公开(公告)日:2023-04-13
申请号:US17836831
申请日:2022-06-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: SUJEONG KIM , BONGSOON LIM , HONGSOO JEON
IPC: H01L27/11575 , H01L27/11519 , H01L27/11556 , H01L27/11548 , H01L27/11565 , H01L27/11582
Abstract: A semiconductor device may include stacks extended in a first direction on a substrate, separation structures extended in the first direction and respectively provided between the stacks, vertical channels penetrating each of the stacks, bit lines extended in a second direction crossing the first direction, each of the vertical channels being overlapped with a pair of the bit lines, and contact plugs connecting the bit lines to the vertical channels. Each of the stacks may include electrodes stacked on the substrate and at least two upper separation patterns dividing an upper one of the electrodes into several portions in the second direction. The vertical channels may be classified into a plurality of types, depending on a distance from one of the separation structures in the second direction, and each of the bit lines may be connected to all types of the vertical channels.
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公开(公告)号:US20230056261A1
公开(公告)日:2023-02-23
申请号:US17982255
申请日:2022-11-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: BONGSOON LIM , SANG-WAN NAM , SANG-WON PARK , SANG-WON SHIM , HONGSOO JEON , YONGHYUK CHOI
IPC: H01L23/535 , H01L27/11573 , H01L27/11582
Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
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公开(公告)号:US20200243140A1
公开(公告)日:2020-07-30
申请号:US16846539
申请日:2020-04-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: BONGSOON LIM , JUNG-YUN YUN , JI-SUK KIM , SANG-WON PARK
Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.
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公开(公告)号:US20220270689A1
公开(公告)日:2022-08-25
申请号:US17742142
申请日:2022-05-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: SANGWON SHIM , SANGWON PARK , BONGSOON LIM , YOONHEE CHOI
IPC: G11C16/30 , G11C5/14 , H01L23/00 , H01L25/065 , H01L25/18
Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery.
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公开(公告)号:US20200168547A1
公开(公告)日:2020-05-28
申请号:US16592886
申请日:2019-10-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: BONGSOON LIM , SANG-WAN NAM , SANG-WON PARK , SANG-WON SHIM , HONGSOO JEON , YONGHYUK CHOI
IPC: H01L23/535 , H01L27/11582 , H01L27/11573
Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
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公开(公告)号:US20190157292A1
公开(公告)日:2019-05-23
申请号:US15996483
申请日:2018-06-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: CHANHO KIM , PANSUK KWAK , CHAEHOON KIM , HONGSOO JEON , JEUNGHWAN PARK , BONGSOON LIM
IPC: H01L27/11582 , G11C16/04 , H01L27/1157 , G11C16/24
Abstract: At least one latch of a page buffer of a nonvolatile memory device includes a capacitor that selectively stores a voltage of a sensing node. The capacitor includes at least one first contact having a second height corresponding to a first height of each of cell strings, and at least one second contact to which a ground voltage is supplied. The at least one second contact has a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact.
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