THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

    公开(公告)号:US20210005629A1

    公开(公告)日:2021-01-07

    申请号:US17025479

    申请日:2020-09-18

    Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.

    MEMORY DEVICE HAVING DIFFERENT NUMBERS OF BITS STORED IN MEMORY CELLS

    公开(公告)号:US20210043244A1

    公开(公告)日:2021-02-11

    申请号:US16810527

    申请日:2020-03-05

    Abstract: A memory device includes word lines stacked on an upper surface of a substrate, channel structures penetrating through the word lines, and each including channel regions connected to one another in a first direction perpendicular to the upper surface of the substrate, and word-line cuts extending in the first direction and dividing the word lines to blocks. The word lines and the channel structures provide memory cell strings, and each of the memory cell strings include memory cells arranged in the first direction. The memory cells included in at least one of the memory cell strings include a first memory cell and a second memory cell disposed at different positions in the first direction, and the number of bits of data stored in the first memory cell is less than the number of bits of data stored in the second memory cell.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM THEREWITH

    公开(公告)号:US20230115503A1

    公开(公告)日:2023-04-13

    申请号:US17836831

    申请日:2022-06-09

    Abstract: A semiconductor device may include stacks extended in a first direction on a substrate, separation structures extended in the first direction and respectively provided between the stacks, vertical channels penetrating each of the stacks, bit lines extended in a second direction crossing the first direction, each of the vertical channels being overlapped with a pair of the bit lines, and contact plugs connecting the bit lines to the vertical channels. Each of the stacks may include electrodes stacked on the substrate and at least two upper separation patterns dividing an upper one of the electrodes into several portions in the second direction. The vertical channels may be classified into a plurality of types, depending on a distance from one of the separation structures in the second direction, and each of the bit lines may be connected to all types of the vertical channels.

    NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE

    公开(公告)号:US20200243140A1

    公开(公告)日:2020-07-30

    申请号:US16846539

    申请日:2020-04-13

    Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.

    MEMORY DEVICE
    8.
    发明申请

    公开(公告)号:US20220270689A1

    公开(公告)日:2022-08-25

    申请号:US17742142

    申请日:2022-05-11

    Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery.

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