公开(公告)号：US20170301388A1

公开(公告)日：2017-10-19

申请号：US15640854

申请日：2017-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEHYUNG LEE ,  JungSik KIM ,  YOUNGDAE LEE ,  DUYEUL KIM ,  SUNGMIN YIM ,  KWANGIL PARK ,  CHULSUNG PARK

IPC: G11C11/4072 ,  G11C11/408 ,  G11C11/409 ,  G11C5/04 ,  H01L23/498 ,  G11C29/50 ,  G11C29/02 ,  H01L25/065 ,  G11C7/10

CPC classification number: G11C11/4072 ,  G11C5/04 ,  G11C7/1063 ,  G11C7/1075 ,  G11C7/109 ,  G11C11/408 ,  G11C11/409 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  H01L23/49838 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

公开(公告)号：US20220358987A1

公开(公告)日：2022-11-10

申请号：US17872720

申请日：2022-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEHYUNG LEE ,  JungSik KIM ,  YOUNGDAE LEE ,  DUYEUL KIM ,  SUNGMIN YIM ,  KWANGIL PARK ,  CHULSUNG PARK

IPC: G11C11/4072 ,  H01L25/065 ,  G11C11/408 ,  G11C11/409 ,  H01L23/498 ,  G11C29/02 ,  G11C29/50 ,  G11C5/04

Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

公开(公告)号：US20210210132A1

公开(公告)日：2021-07-08

申请号：US17205832

申请日：2021-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEHYUNG LEE ,  JungSik KIM ,  YOUNGDAE LEE ,  DUYEUL KIM ,  SUNGMIN YIM ,  KWANGIL PARK ,  CHULSUNG PARK

IPC: G11C11/4072 ,  H01L25/065 ,  G11C11/408 ,  G11C11/409 ,  H01L23/498 ,  G11C29/02 ,  G11C29/50 ,  G11C5/04

Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

公开(公告)号：US20140146589A1

公开(公告)日：2014-05-29

申请号：US13832996

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHULSUNG PARK ,  DONGSOO JUN ,  JOOSUN CHOI

IPC: G11C5/02

CPC classification number: G11C11/4076 ,  G06F12/0893 ,  G06F2212/3042 ,  G11C2207/2245

Abstract: A semiconductor memory device is provided which includes a dynamic random access memory including a memory cell array formed of dynamic random access memory cells; a cache memory formed at the same chip as the dynamic random access memory and configured to communicate with a processor or an external device; and a controller connected with the dynamic random access memory and the cache memory in the same chip and configured to control a dynamic random access function and a cache function.

Abstract translation: 提供一种半导体存储器件，其包括动态随机存取存储器，其包括由动态随机存取存储器单元形成的存储单元阵列; 高速缓冲存储器，其形成在与所述动态随机存取存储器相同的芯片处，并被配置为与处理器或外部设备进行通信; 以及与同一芯片中的动态随机存取存储器和高速缓冲存储器连接的控制器，用于控制动态随机存取功能和高速缓存功能。

公开(公告)号：US20200066323A1

公开(公告)日：2020-02-27

申请号：US16674554

申请日：2019-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEHYUNG LEE ,  JungSik KIM ,  YOUNGDAE LEE ,  DUYEUL KIM ,  SUNGMIN YIM ,  KWANGIL PARK ,  CHULSUNG PARK

IPC: G11C11/4072 ,  G11C29/50 ,  G11C11/408 ,  G11C11/409 ,  H01L23/498 ,  G11C5/04 ,  G11C29/02 ,  H01L25/065

Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

公开(公告)号：US20190355407A1

公开(公告)日：2019-11-21

申请号：US16527415

申请日：2019-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEHYUNG LEE ,  JungSik KIM ,  YOUNGDAE LEE ,  DUYEUL KIM ,  SUNGMIN YIM ,  KWANGIL PARK ,  CHULSUNG PARK

IPC: G11C11/4072 ,  G11C29/50 ,  G11C11/408 ,  G11C11/409 ,  H01L23/498 ,  G11C5/04 ,  H01L25/065 ,  G11C29/02

Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

公开(公告)号：US20160125931A1

公开(公告)日：2016-05-05

申请号：US14827686

申请日：2015-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUYEON DOO ,  TAEYOUNG OH ,  NAMJONG KIM ,  CHULSUNG PARK

IPC: G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/40626 ,  G11C11/406

Abstract: A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change.

Abstract translation: 一种半导体存储器件包括包括多个存储单元和刷新控制电路的存储器电路。 刷新控制电路被配置为响应于模式寄存器组（MRS）代码信号来确定执行目标行刷新（TRR）的次数，其中响应于温度变化而产生MRS代码信号，并且 刷新控制电路被配置为在由于温度变化而改变刷新周期的一段时间内保持至少两个存储单元的刷新周期。