公开(公告)号：US20210143096A1

公开(公告)日：2021-05-13

申请号：US17038521

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwa YUN ,  Chan Ho KIM ,  Dong Ku KANG ,  Bong Soon LIM

IPC: H01L23/522 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure disposed on a first substrate, a horizontal semiconductor layer disposed on a second substrate, a plurality of stack structures on the horizontal semiconductor layer in a first direction, wherein the plurality of stack structures include a memory cell region and a capacitor region, a plurality of electrode isolation regions extending in the first direction and a second direction and configured to separate the plurality of stack structures to be connected to the horizontal semiconductor layer and a plurality of through-via structures having a first side connected to a through channel contact through at least one metal pad, wherein a capacitor is formed between each of electrode pads and at least one of electrode isolation regions in the plurality of stack structures or at least one of the plurality of through-via structures.

公开(公告)号：US20130238843A1

公开(公告)日：2013-09-12

申请号：US13862817

申请日：2013-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan Ho KIM ,  Dong Kyu YOUN ,  Sang Won HWANG ,  Jin Yub LEE

IPC: G11C8/12 ,  G11C16/08

CPC classification number: G11C8/12 ,  G11C16/0483 ,  G11C16/08

Abstract: A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address.

Abstract translation: 非易失性存储器件包括第一垫，第二垫，第三垫，第一地址解码器，第二地址解码器和第三地址解码器。 第一垫包括第一存储块，第二垫包括第二存储块，第三块包括第三存储块。 第一地址解码器根据第一偶数地址选择第一存储块之一，第二地址解码器根据第二偶数地址或第一奇数地址选择第二存储块之一，并且第三地址解码器选择 第三存储器块根据第二奇数地址。

公开(公告)号：US20210143162A1

公开(公告)日：2021-05-13

申请号：US16886898

申请日：2020-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwa YUN ,  Chan Ho KIM ,  Dong Ku KANG ,  Bong Soon LIM

IPC: H01L27/11526 ,  H01L27/11519 ,  H01L23/522 ,  G11C16/08 ,  G11C16/24 ,  H01L27/11556

Abstract: A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure on a substrate and including a peripheral circuits, horizontal semiconductor layers on the peripheral logic structure, a stack structures in which mold layers and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layers, electrode isolation regions separating the stack structures and extending in the first direction and a second direction, the electrode isolation regions being connected to the horizontal semiconductor layers, and through-via structures in the peripheral logic structure. The through-via structures penetrate the stack structures in the first direction. Each of the through-via structures have one side connected to a corresponding one of the through channel contacts. Capacitors are formed by electrode pads respectively with at least one of the electrode isolation regions or with at least one of the through-via structures.

公开(公告)号：US20210193679A1

公开(公告)日：2021-06-24

申请号：US16993570

申请日：2020-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hong KWON ,  Chan Ho KIM ,  Kyung Hwa YUN ,  Dae Seok BYEON ,  Chi Weon YOON

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  G11C5/14 ,  G11C16/08 ,  G11C16/24 ,  G11C16/32

Abstract: Provided is a semiconductor memory device. In order to permit dense integration of a high number of stacked word lines in the semiconductor memory device, a charge pump is included in the semiconductor Mary device. The charge pump makes use of a capacitor. The capacitor is implemented with respect to the dense integration. Some components are placed under the stacked word lines, and some are not under the stacked word lines. The capacity of the capacitor not under the stacked word lines is provided in part by a parallel structure.