公开(公告)号：US09466724B2

公开(公告)日：2016-10-11

申请号：US14704485

申请日：2015-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changjae Yang ,  Shigenobu Maeda ,  Changhwa Kim ,  Youngmoon Choi

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L29/7853 ,  H01L29/045 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: According to an exemplary embodiment of the present embodiment, a semiconductor device is provided as follows. An active fin protrudes from a substrate, extending in a direction. A gate structure crosses a first region of the active fin. A source/drain is disposed on a second region of the active fin. The source/drain includes upper surfaces and vertical side surfaces. The vertical side surfaces are in substantially parallel with side surfaces of the active fin.

Abstract translation: 根据本实施例的示例性实施例，提供如下的半导体器件。 主动翅片从沿着方向延伸的基底突出。 栅极结构与有源鳍片的第一区域交叉。 源极/漏极设置在有源鳍片的第二区域上。 源极/漏极包括上表面和垂直侧面。 垂直侧表面基本上平行于活动翅片的侧表面。

公开(公告)号：US09287401B2

公开(公告)日：2016-03-15

申请号：US14469615

申请日：2014-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwan Lee ,  Sangsu Kim ,  Changjae Yang

IPC: H01L21/76 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/785

Abstract: A field effect transistor includes a fin structure, having a sidewall, protruding from a substrate, and a device isolation structure on the substrate, the device isolation structure defining the sidewall of the fin structure, wherein the fin structure includes a buffer semiconductor pattern disposed on the substrate and a channel pattern disposed on the buffer semiconductor pattern, wherein the buffer semiconductor pattern has a lattice constant different from that of the channel pattern, and wherein the device isolation structure includes a gap-fill insulating layer, and includes an oxidation blocking layer pattern disposed between the buffer semiconductor pattern and the gap-fill insulating layer.

Abstract translation: 场效应晶体管包括翅片结构，其具有从衬底突出的侧壁和衬底上的器件隔离结构，所述器件隔离结构限定鳍结构的侧壁，其中鳍结构包括布置在 所述衬底和布置在所述缓冲半导体图案上的沟道图案，其中所述缓冲半导体图案具有与所述沟道图案不同的晶格常数，并且其中所述器件隔离结构包括间隙填充绝缘层，并且包括氧化阻挡层 设置在缓冲半导体图案和间隙填充绝缘层之间的图案。

公开(公告)号：US09362397B2

公开(公告)日：2016-06-07

申请号：US14464785

申请日：2014-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gi Hur ,  Sangsu Kim ,  Junggil Yang ,  Changjae Yang ,  Dongkyu Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/12

CPC classification number: H01L29/7832 ,  H01L27/1104 ,  H01L29/12 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/7831

Abstract: A gate-all-around (GAA) semiconductor device can include a fin structure that includes alternatingly layered first and second semiconductor patterns. A source region can extend into the alternatingly layered first and second semiconductor patterns and a drain region can extend into the alternatingly layered first and second semiconductor patterns. A gate electrode can extend between the source region and the drain region and surround channel portions of the second semiconductor patterns between the source region and the drain region to define gaps between the source and drain regions. A semiconductor oxide can be on first side walls of the gap that face the source and drain regions and can be absent from at least one of second side walls of the gaps that face the second semiconductor patterns. A gate insulating layer can be on the first side walls of the gaps between the gate electrode and the semiconductor oxide.

Abstract translation: 栅极全能（GAA）半导体器件可以包括鳍结构，其包括交替分层的第一和第二半导体图案。 源极区域可以延伸到交替层叠的第一和第二半导体图案中，并且漏极区域可以延伸到交替层叠的第一和第二半导体图案中。 栅电极可以在源极区域和漏极区域之间延伸并且围绕源极区域和漏极区域之间的第二半导体图案的通道部分，以限定源极和漏极区域之间的间隙。 半导体氧化物可以位于与源极和漏极区域相对的间隙的第一侧壁上，并且可以不存在面对第二半导体图案的间隙的第二侧壁中的至少一个。 栅极绝缘层可以位于栅电极和半导体氧化物之间的间隙的第一侧壁上。

公开(公告)号：US20150084041A1

公开(公告)日：2015-03-26

申请号：US14464785

申请日：2014-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gi Hur ,  Sangsu Kim ,  Junggil Yang ,  Changjae Yang ,  Dongkyu Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/12

CPC classification number: H01L29/7832 ,  H01L27/1104 ,  H01L29/12 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/7831

Abstract: A gate-all-around (GAA) semiconductor device can include a fin structure that includes alternatingly layered first and second semiconductor patterns. A source region can extend into the alternatingly layered first and second semiconductor patterns and a drain region can extend into the alternatingly layered first and second semiconductor patterns. A gate electrode can extend between the source region and the drain region and surround channel portions of the second semiconductor patterns between the source region and the drain region to define gaps between the source and drain regions. A semiconductor oxide can be on first side walls of the gap that face the source and drain regions and can be absent from at least one of second side walls of the gaps that face the second semiconductor patterns. A gate insulating layer can be on the first side walls of the gaps between the gate electrode and the semiconductor oxide.

Abstract translation: 栅极全能（GAA）半导体器件可以包括鳍结构，其包括交替分层的第一和第二半导体图案。 源极区域可以延伸到交替层叠的第一和第二半导体图案中，并且漏极区域可以延伸到交替层叠的第一和第二半导体图案中。 栅电极可以在源极区域和漏极区域之间延伸并且围绕源极区域和漏极区域之间的第二半导体图案的通道部分，以限定源极和漏极区域之间的间隙。 半导体氧化物可以位于与源极和漏极区域相对的间隙的第一侧壁上，并且可以不存在面对第二半导体图案的间隙的第二侧壁中的至少一个。 栅极绝缘层可以位于栅电极和半导体氧化物之间的间隙的第一侧壁上。