公开(公告)号：US20220093470A1

公开(公告)日：2022-03-24

申请号：US17536580

申请日：2021-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheonsu LEE ,  Rohitaswa BHATTACHARYA

IPC: H01L21/8234 ,  H01L29/51 ,  H01L27/088 ,  H01L21/28

Abstract: An electronic system may include one or more units of processing circuitry configured to implement a main intellectual property (IP), a checker IP, and an error detection circuit. The main IP includes a first data path and a first control signal path. The checker IP includes a second control signal path. The error detection circuit is configured to detect an error of data by performing error correction code (ECC) decoding of output data that is output by the main IP to the error detection circuit through the first data path, and detect an error of a control signal based on a first signal that is output by the main IP to the error detection circuit through the first control signal path, and a second signal that is output by the checker IP to the error detection circuit through the second control signal path.

公开(公告)号：US20210149765A1

公开(公告)日：2021-05-20

申请号：US16939310

申请日：2020-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheonsu LEE ,  Rohitaswa BHATTACHARYA

IPC: G06F11/10 ,  G06F13/16

Abstract: An electronic system may include one or more units of processing circuitry configured to implement a main intellectual property (IP), a checker IP, and an error detection circuit. The main IP includes a first data path and a first control signal path. The checker IP includes a second control signal path. The error detection circuit is configured to detect an error of data by performing error correction code (ECC) decoding of output data that is output by the main IP to the error detection circuit through the first data path, and detect an error of a control signal based on a first signal that is output by the main IP to the error detection circuit through the first control signal path, and a second signal that is output by the checker IP to the error detection circuit through the second control signal path.