公开(公告)号：US20230168707A1

公开(公告)日：2023-06-01

申请号：US17846289

申请日：2022-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongeui LEE ,  Hyungjin KIM ,  Jonghyun JANG ,  Chulseung LEE

IPC: G06F1/08 ,  G06F1/10

CPC classification number: G06F1/08 ,  G06F1/10

Abstract: A memory controller for a memory device, the memory controller including: a command generator configured to generate a command signal based on a system clock signal, and to generate phase difference information for the command signal; and a memory interface configured to receive the command signal and the phase difference information from the command generator, to adjust a timing of the command signal based on the phase difference information, and transmit the command signal of which the timing is adjusted as a timing adjusted command signal to the memory device.

公开(公告)号：US20160118088A1

公开(公告)日：2016-04-28

申请号：US14919068

申请日：2015-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulseung LEE ,  Kyuwook HAN ,  Jake EU

IPC: G11C7/10 ,  G11C8/06 ,  G11C7/22

CPC classification number: G11C8/06 ,  G06F2212/7208 ,  G11C8/12 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20

Abstract: A storage device includes first and second nonvolatile memory groups that respectively include first and second nonvolatile memory chips, a memory controller connected to the first and second nonvolatile memory groups in common through input/output lines and at least one control line, and a group select circuit connected to the memory controller through the at least one control line and chip enable lines. The group select circuit is connected to the first and second nonvolatile memory groups through a plurality of first and second chip enable lines, respectively. The group select circuit, in response to receiving a control signal through the at least one control line, is configured to transmit chip enable signals to a selected memory group among the first nonvolatile memory group and the second nonvolatile memory group through selected chip enable lines among the first chip enable lines and the second chip enable lines.

Abstract translation: 存储装置包括分别包括第一和第二非易失性存储器芯片的第一和第二非易失性存储器组，通过输入/输出线和至少一个控制线连接到第一和第二非易失性存储器组的存储器控​​制器，以及组选择 电路通过至少一个控制线和芯片使能线连接到存储器控制器。 组选择电路分别通过多个第一和第二芯片使能线连接到第一和第二非易失性存储器组。 组选择电路响应于通过至少一个控制线接收控制信号，被配置为通过所选择的芯片使能线在第一非易失性存储器组和第二非易失性存储器组之间向选定的存储器组发送芯片使能信号， 第一芯片使能线和第二芯片使能线。

公开(公告)号：US20190080730A1

公开(公告)日：2019-03-14

申请号：US15962206

申请日：2018-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulseung LEE ,  ChoongEui LEE ,  Soon Suk HWANG ,  Kyuwook HAN

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C29/02 ,  G06F13/16

Abstract: Disclosed is a storage device. The storage device includes a nonvolatile memory device that receives write data based on a data strobe signal and a data signal and outputs read data based on the data strobe signal and the data signal, and a controller that performs a training operation for training the nonvolatile memory device to align the data signal and the data strobe signal. The controller detects a left edge of a window of the data signal for the training operation. The controller determines a center of the window by using the detected left edge and unit interval length information of the data signal or determines a start point of a detection operation for detecting a right edge of the window by using the detected left edge and the unit interval length information.