公开(公告)号：US20190172509A1

公开(公告)日：2019-06-06

申请号：US16045887

申请日：2018-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONG-SEOK KANG ,  Byung-Chul Kim

IPC: G11C7/22 ,  G06F3/06

Abstract: A memory device performs first training including a plurality of loop operations to align a main clock signal and a data clock signal, which are received from a memory controller. A method of operating the memory device includes generating division ratio information indicating a division ratio set based on a frequency ratio of the main clock signal to the data clock signal and transmitting the division ratio information to the memory controller to perform the first training. A first loop operation includes: receiving first phase control information, which is generated based on the division ratio information, from the memory controller, dividing the data clock signal based on the division ratio to generate a division data clock signal, selecting a first phase from among a plurality of phases based on the first phase control information, generating a first comparison target clock signal that is shifted from the division data clock signal by the first phase, comparing a phase of the first comparison target clock signal with a phase of the main clock signal, and transmitting a first phase comparison result to the memory controller.

公开(公告)号：US20190180797A1

公开(公告)日：2019-06-13

申请号：US16054633

申请日：2018-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-JU KIM ,  DONG-SEOK KANG ,  HYE JUNG KWON ,  BYUNGCHUL KIM ,  SEUNGJUN BAE

IPC: G11C7/10 ,  G11C11/4076 ,  G11C8/18 ,  G11C11/408 ,  G11C11/4096 ,  H03L7/08

Abstract: A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.

公开(公告)号：US20190018737A1

公开(公告)日：2019-01-17

申请号：US15938092

申请日：2018-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONG-HUN KIM ,  SU-YEON DOO ,  DONG-SEOK KANG ,  HYE-JUNG KWON ,  YOUNG-JU KIM

IPC: G06F11/14 ,  H03K3/84 ,  G06F11/10

Abstract: A memory device includes an output pin, a mode register, a signal generator configured to generate a detection clock output signal including one of a random data pattern and a hold data pattern in response to first and second control signals from the mode register, and output the detection clock output signal through the output pin. The random data pattern includes pseudo-random data generated by the memory device. The hold data pattern is a fixed pattern pre stored in the memory device. The detection clock output signal is used for a clock and data recovery operation.