公开(公告)号：US20170032754A1

公开(公告)日：2017-02-02

申请号：US15187920

申请日：2016-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONG-HUN KIM ,  HYUNSANG PARK ,  KYUNGCHUN KIM ,  JAE-BUM LEE

IPC: G09G3/36 ,  H03M1/06 ,  H03M1/66

CPC classification number: G09G3/3648 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2310/08 ,  G09G2320/0247 ,  H03M1/0607 ,  H03M1/66

Abstract: A digital-to-analog converter includes an amplifier including at least two input terminals corresponding to a non-inverting input terminal; and a chopping unit performing a chopping operation between voltages provided to the at least two input terminals corresponding to the non-inverting input terminal. The digital-to-analog converter has an X+Y bit structure and removes an offset by performing an interpolation chopping operation and/or a main buffer chopping operation at the same time. The digital-to-analog structure can be embodied in a small area and can process high bit image data.

Abstract translation: 数模转换器包括：放大器，包括对应于非反相输入端的至少两个输入端; 以及斩波单元，在提供给对应于所述非反相输入端子的所述至少两个输入端子的电压之间进行斩波操作。 数模转换器具有X + Y位结构，并且通过同时执行插值斩波操作和/或主缓冲器斩波操作来消除偏移。 数模比结构可以体现在一个小区域中，并且可以处理高位图像数据。

公开(公告)号：US20230111814A1

公开(公告)日：2023-04-13

申请号：US17950599

申请日：2022-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHAN LEE ,  YONG-HUN KIM

IPC: G09G3/3275 ,  G09G3/20

Abstract: A column driver integrated circuit (IC) which drives a first group of pixel lines connected to a first group of pixels included in a display panel, and a second group of pixel lines connected to a second group of pixels included in the display panel, the column driver IC including: a master gray scale voltage generation circuit configured to divide a reference voltage to generate tap voltages, and to generate a first low-power mode gray scale voltage based on at least one of the tap voltages; and a first low-power mode amplifier configured to drive the first group of pixel lines based on the first low-power mode gray scale voltage.

公开(公告)号：US20190018737A1

公开(公告)日：2019-01-17

申请号：US15938092

申请日：2018-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONG-HUN KIM ,  SU-YEON DOO ,  DONG-SEOK KANG ,  HYE-JUNG KWON ,  YOUNG-JU KIM

IPC: G06F11/14 ,  H03K3/84 ,  G06F11/10

Abstract: A memory device includes an output pin, a mode register, a signal generator configured to generate a detection clock output signal including one of a random data pattern and a hold data pattern in response to first and second control signals from the mode register, and output the detection clock output signal through the output pin. The random data pattern includes pseudo-random data generated by the memory device. The hold data pattern is a fixed pattern pre stored in the memory device. The detection clock output signal is used for a clock and data recovery operation.