公开(公告)号：US20220122675A1

公开(公告)日：2022-04-21

申请号：US17379109

申请日：2021-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TongSung KIM ,  Dae Hoon NA ,  Jung-June PARK ,  Dong Ho SHIN ,  Byung Hoon JEONG ,  Young Min JO

IPC: G11C16/32 ,  H01L25/18 ,  H01L25/065 ,  G11C16/04 ,  G11C16/26 ,  G06F3/06 ,  G06F1/10

Abstract: A storage system includes: a memory controller which provides a clock signal; a buffer which receives the clock signal and re-drives the clock signal, the buffer including a sampler which receives a data signal and a data strobe signal regarding the data signal, and which outputs a data stream; and a nonvolatile memory, including: a first duty cycle corrector, which receives the clock signal outputs a corrected clock signal by performing a first duty correction operation on the clock signal; and a data strobe signal generator, which generates the data strobe signal based on the corrected clock signal and provides the data strobe signal to the buffer. The buffer receives the data strobe signal output from the nonvolatile memory, senses a duty ratio of the data strobe signal input to the sampler, and performs a second duty correction operation on the duty ratio of the input data strobe signal.

公开(公告)号：US20200227131A1

公开(公告)日：2020-07-16

申请号：US16537970

申请日：2019-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Hoon NA ,  Jang Woo LEE ,  Jin Do BYUN ,  Jeong Don IHM

IPC: G11C29/50 ,  H01L25/065 ,  H01L25/18

Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.

公开(公告)号：US20230335203A1

公开(公告)日：2023-10-19

申请号：US18212825

申请日：2023-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TongSung KIM ,  Dae Hoon NA ,  Jung-June PARK ,  Dong Ho SHIN ,  Byung Hoon JEONG ,  Young Min JO

IPC: G06F1/10 ,  G11C16/26 ,  G11C16/32 ,  G06F3/06 ,  G11C16/04 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C16/32 ,  G06F1/10 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/26 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06562

Abstract: A storage system includes a memory controller providing a clock signal; a buffer having a first duty cycle corrector to receive the clock signal and a chip selection signal from the memory controller, perform a first duty correction operation on the clock signal using a first data code and output a first corrected clock signal, a register to store the first data code regarding the chip selection signal, and a sampler to receive a data signal and a data strobe signal regarding the data signal and output a data stream; and a nonvolatile memory having a second duty cycle corrector to receive the first corrected clock signal from the buffer and perform a second duty correction operation on the first corrected clock signal using a second data code and out a second corrected clock signal, a second data code generation circuit to generate the second data code based on the second corrected clock signal, and a data strobe signal generator to generate the data strobe signal based on the second corrected clock signal and provide the data strobe signal to the buffer.

公开(公告)号：US20200014383A1

公开(公告)日：2020-01-09

申请号：US16206070

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Hoon NA ,  Seon Kyoo LEE ,  Jeong Don IHM ,  Byung Hoon JEONG ,  Young Don CHOI

IPC: H03K17/22 ,  H01L25/065 ,  H01L23/48

Abstract: A semiconductor package including a first master-slave status circuit configured to store one of a first signal or a second signal independently from a second master-slave status circuit, store the first signal in response to receiving a first initial signal from a first initialization circuit, the second master-slave status circuit configured to store one of the first signal or the second signal, store the first signal in response to receiving a second initial signal from a second initialization circuit, the first initialization circuit configured to provide the first initial signal to the first master-slave status circuit, the second initialization circuit configured to provide the second initial signal to the second master-slave status circuit, and a first master-slave determination circuit connected to the second master-slave status circuit, the first master-slave determination circuit configured to provide the second signal to the second master-slave status circuit may be provided.