公开(公告)号：US20250117257A1

公开(公告)日：2025-04-10

申请号：US18830998

申请日：2024-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungmin AHN ,  Hong Rak SON ,  Dong-Min SHIN ,  Dae-Yeol YANG ,  JongYoon YOON ,  Jae Hun JANG ,  Se Jung KWON ,  Byeongwook KIM ,  Baeseong PARK ,  Dongsoo LEE

IPC: G06F9/50 ,  H03M13/00 ,  H03M13/13

Abstract: Disclosed is an accelerator device which includes an interface circuit that communicates with an external device, a memory that stores first data received through the interface circuit, a polar encoder that performs polar encoding with respect to the first data provided from the memory and to output a result of the polar encoding as second data, and an accelerator core that loads the second data. The first data are compressed weight data, the second data are decompressed weight data, the accelerator core is configured to perform machine learning-based inference based on the second data, and the first data are variable in length.

公开(公告)号：US20250125820A1

公开(公告)日：2025-04-17

申请号：US18628043

申请日：2024-04-05

Applicant: SAMSUNG ELECTRONICS CO,. LTD,

Inventor： Dae-Yeol YANG ,  Dong-Min Shin ,  Bohwan Jun ,  Youngjun Hwang

IPC: H03M13/11 ,  H03M13/25

Abstract: A storage device is provided. The storage device includes: a nonvolatile memory device; and a controller configured to: receive first data from the nonvolatile memory device; perform first error correction decoding with respect to the first data to obtain second data; control an error correction capability and an error detection capability of second error correction decoding based on information about the first error correction decoding; and perform the second error correction decoding with respect to the second data based on the error correction capability and the error detection capability to obtain third data.

公开(公告)号：US20240340025A1

公开(公告)日：2024-10-10

申请号：US18520707

申请日：2023-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijun JEON ,  Kyoungbin PARK ,  Hong Rak SON ,  Dae-Yeol YANG ,  Geunyeong YU ,  Bohwan JUN ,  Youngjun HWANG

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1168 ,  H03M13/616

Abstract: A semiconductor device may include an error correcting code (ECC) encoder that encodes a codeword based on a parity check matrix and generates the encoded codeword including an information bit and a parity bit. The parity check matrix is divided into an information part corresponding to the information bit and a parity part corresponding to the parity bit. The parity part includes a block matrix T including a plurality of first sub-matrices arranged in a dual diagonal structure, a block matrix B including a first sub-matrix and a (1−a)-th sub-matrix, a block matrix D composed of a first sub-matrix, and a block matrix E including a first sub-matrix and a masked (1−(a+1))-th sub-matrix. A location where the first sub-matrix is placed in the block matrix B precedes a location where the masked (1−(a+1))-th sub-matrix is placed in the block matrix E.