公开(公告)号：US20210149762A1

公开(公告)日：2021-05-20

申请号：US16914890

申请日：2020-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangseok LEE ,  Dong-min SHIN ,  Geunyeoung YU ,  Bohwan JUN ,  Hee Youl KWAK ,  Hong Rak SON

IPC: G06F11/10 ,  H03M13/11 ,  H03M13/35

Abstract: An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

公开(公告)号：US20240120945A1

公开(公告)日：2024-04-11

申请号：US18225313

申请日：2023-07-24

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Daeyeol YANG ,  Bohwan JUN ,  Hongrak SON ,  Geunyeong YU ,  Youngjun HWANG

IPC: H03M13/11

CPC classification number: H03M13/116 ,  H03M13/1108 ,  H03M13/1177

Abstract: A generalized low-density parity-check (G-LDPC) encoder, including a plurality of generalized constraint (GC) encoders configured to perform a plurality of GC encoding operations in parallel based on a GC code having a quasi-cyclic (QC) structure including information variable nodes, inner parity variable nodes, and super check nodes configured to perform multiple condition checks, wherein each GC encoder of the plurality of GC encoders includes a plurality of first logic circuits configured to perform a GC encoding operation of the plurality of GC encoding operations; and an LDPC encoder configured to perform an LDPC encoding operation based on an LDPC code having the QC structure, wherein the LDPC encoder includes a plurality of single check nodes configured to perform a single parity check, wherein the each GC encoder is configured to receive information bits, and to determine parity bits of a portion of inner parity bits corresponding to the information bits by enabling only a portion of the plurality of first logic circuits to perform the GC encoding operation, and wherein the LDPC encoder is configured to: obtain the inner parity bits by combining the parity bits obtained from the plurality of GC encoders, determine outer parity bits corresponding to the information bits and the inner parity bits by performing the LDPC encoding operation, and output the information bits, the inner parity bits, and the outer parity bits as a codeword.

公开(公告)号：US20240340025A1

公开(公告)日：2024-10-10

申请号：US18520707

申请日：2023-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijun JEON ,  Kyoungbin PARK ,  Hong Rak SON ,  Dae-Yeol YANG ,  Geunyeong YU ,  Bohwan JUN ,  Youngjun HWANG

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1168 ,  H03M13/616

Abstract: A semiconductor device may include an error correcting code (ECC) encoder that encodes a codeword based on a parity check matrix and generates the encoded codeword including an information bit and a parity bit. The parity check matrix is divided into an information part corresponding to the information bit and a parity part corresponding to the parity bit. The parity part includes a block matrix T including a plurality of first sub-matrices arranged in a dual diagonal structure, a block matrix B including a first sub-matrix and a (1−a)-th sub-matrix, a block matrix D composed of a first sub-matrix, and a block matrix E including a first sub-matrix and a masked (1−(a+1))-th sub-matrix. A location where the first sub-matrix is placed in the block matrix B precedes a location where the masked (1−(a+1))-th sub-matrix is placed in the block matrix E.

公开(公告)号：US20220130485A1

公开(公告)日：2022-04-28

申请号：US17244195

申请日：2021-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun HWANG ,  Heeyoul KWAK ,  Bohwan JUN ,  Hongrak SON ,  Dongmin SHIN ,  Geunyeong YU

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C16/10 ,  G11C16/26

Abstract: A memory device includes a cell array including a plurality of pages and a control logic configured to control program and read operations of the cell array. The control logic controls the program and read operations to store first through N-th codewords in a first page among the pages and program a page parity corresponding in common to the first through N-th codewords to the first page in response to a program command for a page unit and to selectively read the first codeword among the first through N-th codewords in response to a read command for a sub-page unit, where N is an integer of at least 2. The first codeword includes first sub-page data and a first sub-parity corresponding thereto, and the first sub-parity includes information for correcting an error in the first sub-page data through error correction code (ECC) decoding independently performed on each codeword.

公开(公告)号：US20220004458A1

公开(公告)日：2022-01-06

申请号：US17480560

申请日：2021-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangseok LEE ,  Dong-min SHIN ,  Geunyeong YU ,  Bohwan JUN ,  Hee Youl KWAK ,  Hong Rak SON

IPC: G06F11/10 ,  H03M13/35 ,  H03M13/11 ,  H03M13/37

Abstract: An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.