Semiconductor devices having bit line insulating capping patterns and multiple conductive patterns thereon
    1.
    发明授权
    Semiconductor devices having bit line insulating capping patterns and multiple conductive patterns thereon 有权
    具有位线绝缘封盖图案和其上的多个导电图案的半导体器件

    公开(公告)号:US08766356B2

    公开(公告)日:2014-07-01

    申请号:US13900910

    申请日:2013-05-23

    Abstract: A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed.

    Abstract translation: 提供了能够减小厚度的半导体器件,采用该半导体器件的电子产品及其制造方法。 制造半导体器件的方法包括制备具有第一和第二有源区的半导体衬底。 第一有源区中的第一晶体管包括第一栅极图案和第一杂质区域。 第二晶体管,第二有源区包括第二栅极图案和第二杂质区域。 第一导电图案在第一晶体管上,其中第一导电图案的至少一部分设置在与半导体衬底的上表面相同的距离处,作为第二栅极图案的至少一部分。 第一导电图案可以形成在第一晶体管上,而形成第二晶体管。

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