Semiconductor light emitting device and semiconductor light emitting apparatus having the same
    1.
    发明授权
    Semiconductor light emitting device and semiconductor light emitting apparatus having the same 有权
    半导体发光器件和具有该半导体发光器件的半导体发光器件

    公开(公告)号:US09196812B2

    公开(公告)日:2015-11-24

    申请号:US14543481

    申请日:2014-11-17

    Abstract: In example embodiments, a semiconductor light emitting device includes a light emitting structure, first and second insulating layers, a barrier metal layer, and an electrode. The light emitting structure includes an active layer between a first and second conductivity-type semiconductor layer. The first insulating layer is on the light emitting structure and defines a first one and a second one of first openings that respectively expose the first and second conductivity-type semiconductor layers. The barrier metal layer is on the first insulating layer and electrically connected to the first and second conductivity-type semiconductor layers through the first and second one of the first openings. The second insulating layer is on the barrier metal layer and defines a second opening that partially exposes the barrier metal layer. The electrode is on the barrier metal layer and electrically connected to the first and second conductivity-type semiconductor layers through the barrier metal layer.

    Abstract translation: 在示例性实施例中,半导体发光器件包括发光结构,第一和第二绝缘层,阻挡金属层和电极。 发光结构包括在第一和第二导电类型半导体层之间的有源层。 第一绝缘层位于发光结构上并且限定分别暴露第一和第二导电类型半导体层的第一开口和第二开口中的第一绝缘层。 阻挡金属层位于第一绝缘层上,并通过第一和第二开口与第一和第二导电型半导体层电连接。 第二绝缘层位于阻挡金属层上并且限定了部分地暴露阻挡金属层的第二开口。 电极在阻挡金属层上,并通过阻挡金属层与第一和第二导电型半导体层电连接。

    Semiconductor devices having bit line insulating capping patterns and multiple conductive patterns thereon
    2.
    发明授权
    Semiconductor devices having bit line insulating capping patterns and multiple conductive patterns thereon 有权
    具有位线绝缘封盖图案和其上的多个导电图案的半导体器件

    公开(公告)号:US08766356B2

    公开(公告)日:2014-07-01

    申请号:US13900910

    申请日:2013-05-23

    Abstract: A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed.

    Abstract translation: 提供了能够减小厚度的半导体器件,采用该半导体器件的电子产品及其制造方法。 制造半导体器件的方法包括制备具有第一和第二有源区的半导体衬底。 第一有源区中的第一晶体管包括第一栅极图案和第一杂质区域。 第二晶体管,第二有源区包括第二栅极图案和第二杂质区域。 第一导电图案在第一晶体管上,其中第一导电图案的至少一部分设置在与半导体衬底的上表面相同的距离处,作为第二栅极图案的至少一部分。 第一导电图案可以形成在第一晶体管上,而形成第二晶体管。

Patent Agency Ranking