公开(公告)号：US11901336B2

公开(公告)日：2024-02-13

申请号：US17355874

申请日：2021-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Dae-woo Kim ,  Eunseok Song

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/24 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/24227 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.

公开(公告)号：US20220139880A1

公开(公告)日：2022-05-05

申请号：US17355874

申请日：2021-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Dae-woo Kim ,  Eunseok Song

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L25/18

Abstract: A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.