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1.发明申请IMAGE SENSOR FOR DISTRIBUTING OUTPUT PEAK CURRENT AND IMAGE PROCESSING SYSTEM INCLUDING THE SAME 有权用于分配输出峰值电流的图像传感器和包括其的图像处理系统公开(公告)号：US20160366359A1
公开(公告)日：2016-12-15
申请号：US14989220
申请日：2016-01-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Han Soo Lee , Hee Sung Chae , Kyung Min Kim , Dah Som Kim , Sun Jung Kim , Seung Hoon Jung
Abstract: The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.
Abstract translation: 图像传感器包括：第一模数转换器，被配置为将从行中的第一像素输出的第一模拟像素信号转换为第一数字信号;第二模数转换器，被配置为将第二模拟像素信号输出 从所述行中的第二像素转换为第二数字信号，第一输出电路，被配置为响应于第一使能控制信号而在第一数字信号中的第一位置处输出第一位值，以及第二输出电路， 响应于第二使能控制信号在第二数字信号中的第二位置处的第二位值，第二数字信号中的第二位置对应于第一数字信号中的第一位置，其中第二使能控制信号由 从第一使能控制信号的激活延迟。
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2.发明授权公开(公告)号：US09819891B2
公开(公告)日：2017-11-14
申请号：US14989220
申请日：2016-01-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Han Soo Lee , Hee Sung Chae , Kyung Min Kim , Dah Som Kim , Sun Jung Kim , Seung Hoon Jung
Abstract: The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.
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