公开(公告)号：US12096147B2

公开(公告)日：2024-09-17

申请号：US17878285

申请日：2022-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Yong Kim ,  Kyung-Min Kim ,  Hyuk Oh ,  Hyeok Jong Lee ,  Seung Hoon Jung ,  Woong Joo ,  Hee Sung Chae

IPC: H04N25/75 ,  H04N25/709 ,  H03M1/56

CPC classification number: H04N25/75 ,  H04N25/709 ,  H03M1/56

Abstract: An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.

公开(公告)号：US09819891B2

公开(公告)日：2017-11-14

申请号：US14989220

申请日：2016-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Soo Lee ,  Hee Sung Chae ,  Kyung Min Kim ,  Dah Som Kim ,  Sun Jung Kim ,  Seung Hoon Jung

IPC: H04N5/378 ,  H03M1/00 ,  H04N5/357

CPC classification number: H04N5/378 ,  H03M1/00 ,  H03M1/123 ,  H03M1/56 ,  H04N5/357

Abstract: The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.

公开(公告)号：US09083368B2

公开(公告)日：2015-07-14

申请号：US13770836

申请日：2013-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Woo Kim ,  Kyoung Min Koh ,  Kyung-Min Kim ,  Hee Sung Chae

IPC: H04N5/335 ,  H03M1/12 ,  H04N5/376 ,  H04N5/378 ,  H03M1/08 ,  H03M1/56

CPC classification number: H03M1/12 ,  H03M1/0863 ,  H03M1/123 ,  H03M1/56 ,  H04N5/3765 ,  H04N5/378

Abstract: An image sensor includes multiple counters and a counter controller. Each counter of the multiple counters is configured to perform counting of a comparison result signal and to generate a count result, the comparison result signal being obtained by comparing a ramp signal and a pixel signal of a column of multiple columns. The counter controller is configured to generate and transmit a counter clock signal and (n−1) delay clock signals to the counters, respectively, “n” being a natural number equal to or greater than two. Each delay clock signal of the (n−1) delay clock signals is obtained by delaying the counter clock signal by a corresponding offset code.

Abstract translation: 图像传感器包括多个计数器和一个计数器控制器。 多个计数器的每个计数器被配置为执行比较结果信号的计数并产生计数结果，比较结果信号是通过比较斜坡信号和多列列的像素信号而获得的。 计数器控制器被配置为分别产生并发送计数器时钟信号和（n-1）个延迟时钟信号给计数器，“n”是等于或大于2的自然数。 通过将计数器时钟信号延迟相应的偏移代码来获得（n-1）个延迟时钟信号的每个延迟时钟信号。

公开(公告)号：US11445139B2

公开(公告)日：2022-09-13

申请号：US16746213

申请日：2020-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Yong Kim ,  Kyung-Min Kim ,  Hyuk Oh ,  Hyeok Jong Lee ,  Seung Hoon Jung ,  Woong Joo ,  Hee Sung Chae

IPC: H04N5/378 ,  H04N5/369 ,  H03M1/56

Abstract: An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.

公开(公告)号：US20160366359A1

公开(公告)日：2016-12-15

申请号：US14989220

申请日：2016-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Soo Lee ,  Hee Sung Chae ,  Kyung Min Kim ,  Dah Som Kim ,  Sun Jung Kim ,  Seung Hoon Jung

IPC: H04N5/378 ,  H04N5/232

CPC classification number: H04N5/378 ,  H03M1/00 ,  H03M1/123 ,  H03M1/56 ,  H04N5/357

Abstract: The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.

Abstract translation: 图像传感器包括：第一模数转换器，被配置为将从行中的第一像素输出的第一模拟像素信号转换为第一数字信号;第二模数转换器，被配置为将第二模拟像素信号输出 从所述行中的第二像素转换为第二数字信号，第一输出电路，被配置为响应于第一使能控制信号而在第一数字信号中的第一位置处输出第一位值，以及第二输出电路， 响应于第二使能控制信号在第二数字信号中的第二位置处的第二位值，第二数字信号中的第二位置对应于第一数字信号中的第一位置，其中第二使能控制信号由 从第一使能控制信号的激活延迟。

公开(公告)号：US10986298B2

公开(公告)日：2021-04-20

申请号：US16657164

申请日：2019-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Hwan Jung ,  Sun Yool Kang ,  Kyung Tae Kim ,  Hee Sung Chae

IPC: H04N5/378

Abstract: A correlated double sampling (CDS) circuit including a comparator, the comparator including: a signal input unit including a first transistor configured to receive a ramp signal and a second transistor configured to receive a pixel signal; and an offset generator unit connected to the signal input unit, the offset generator unit including at least two transistors, wherein in the offset generator unit, an aspect ratio of the at least two transistors in an auto-zeroing period and an aspect ratio of the at least two transistors in a pixel signal decoding period are different from each other.

公开(公告)号：US11706536B2

公开(公告)日：2023-07-18

申请号：US17393803

申请日：2021-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Hong Kim ,  Kyung-Min Kim ,  Hee Sung Chae

IPC: H04N25/60

CPC classification number: H04N25/60

Abstract: An image sensor includes a pixel configured to generate a pixel signal, using an analog signal processing voltage, a ramp signal generator configured to generate a ramp signal, using the analog signal processing voltage, a bias voltage generator configured to generate a bias voltage, using the analog signal processing voltage, and a noise compensator configured to generate a noise component, using a digital signal processing voltage and the analog signal processing voltage, and add the generated noise component to the generated bias voltage. The image sensor further includes a conversion circuit configured to generate a reference voltage, based on the generated ramp signal and the bias voltage to which the noise component is added, and generate an image signal by performing analog-to-digital conversion on the generated pixel signal, based on the generated reference voltage.

公开(公告)号：US11470271B2

公开(公告)日：2022-10-11

申请号：US17032932

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Tae Kim ,  Kyung Min Kim ,  Yun Hwan Jung ,  Hee Sung Chae

IPC: H01L27/146 ,  H03M1/12 ,  H04N5/374 ,  H04N5/357 ,  H04N5/378

Abstract: A pulse generator of an image sensor includes a delay cell including a plurality of transistors arranged in series between a power voltage and a ground, a stabilization capacitor, and a stabilization switch. The power voltage is supplied to a first terminal of a first transistor disposed first among the plurality of transistors, and a gate terminal of the first transistor is connected to a first node. An input voltage is supplied to a gate terminal of an n-th transistor disposed last among the plurality of transistors, and a ground voltage is supplied to a first terminal of the n-th transistor. The stabilization switch is disposed between a reference voltage input terminal providing a reference voltage and the first node. The stabilization switch is turned on by an input bias control signal to supply the reference voltage to the first node.

公开(公告)号：US10812741B2

公开(公告)日：2020-10-20

申请号：US16543016

申请日：2019-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Tae Kim ,  Kyung Min Kim ,  Yun Hwan Jung ,  Hee Sung Chae

IPC: H04N5/357 ,  H04N5/374 ,  H01L27/146 ,  H04N5/378 ,  H03M1/12

Abstract: A pulse generator of an image sensor includes a delay cell including a plurality of transistors arranged in series between a power voltage and a ground, a stabilization capacitor, and a stabilization switch. The power voltage is supplied to a first terminal of a first transistor disposed first among the plurality of transistors, and a gate terminal of the first transistor is connected to a first node. An input voltage is supplied to a gate terminal of an n-th transistor disposed last among the plurality of transistors, and a ground voltage is supplied to a first terminal of the n-th transistor. The stabilization switch is disposed between a reference voltage input terminal providing a reference voltage and the first node. The stabilization switch is turned on by an input bias control signal to supply the reference voltage to the first node.

公开(公告)号：US20200260036A1

公开(公告)日：2020-08-13

申请号：US16657164

申请日：2019-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun Hwan Jung ,  Sun Yool Kang ,  Kyung Tae Kim ,  Hee Sung Chae

IPC: H04N5/378

Abstract: A correlated double sampling (CDS) circuit including a comparator, the comparator including: a signal input unit including a first transistor configured to receive a ramp signal and a second transistor configured to receive a pixel signal; and an offset generator unit connected to the signal input unit, the offset generator unit including at least two transistors, wherein in the offset generator unit, an aspect ratio of the at least two transistors in an auto-zeroing period and an aspect ratio of the at least two transistors in a pixel signal decoding period are different from each other.