公开(公告)号：US12096147B2

公开(公告)日：2024-09-17

申请号：US17878285

申请日：2022-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Yong Kim ,  Kyung-Min Kim ,  Hyuk Oh ,  Hyeok Jong Lee ,  Seung Hoon Jung ,  Woong Joo ,  Hee Sung Chae

IPC: H04N25/75 ,  H04N25/709 ,  H03M1/56

CPC classification number: H04N25/75 ,  H04N25/709 ,  H03M1/56

Abstract: An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.

公开(公告)号：US11445139B2

公开(公告)日：2022-09-13

申请号：US16746213

申请日：2020-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Yong Kim ,  Kyung-Min Kim ,  Hyuk Oh ,  Hyeok Jong Lee ,  Seung Hoon Jung ,  Woong Joo ,  Hee Sung Chae

IPC: H04N5/378 ,  H04N5/369 ,  H03M1/56

Abstract: An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.

公开(公告)号：US20160366359A1

公开(公告)日：2016-12-15

申请号：US14989220

申请日：2016-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Soo Lee ,  Hee Sung Chae ,  Kyung Min Kim ,  Dah Som Kim ,  Sun Jung Kim ,  Seung Hoon Jung

IPC: H04N5/378 ,  H04N5/232

CPC classification number: H04N5/378 ,  H03M1/00 ,  H03M1/123 ,  H03M1/56 ,  H04N5/357

Abstract: The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.

Abstract translation: 图像传感器包括：第一模数转换器，被配置为将从行中的第一像素输出的第一模拟像素信号转换为第一数字信号;第二模数转换器，被配置为将第二模拟像素信号输出 从所述行中的第二像素转换为第二数字信号，第一输出电路，被配置为响应于第一使能控制信号而在第一数字信号中的第一位置处输出第一位值，以及第二输出电路， 响应于第二使能控制信号在第二数字信号中的第二位置处的第二位值，第二数字信号中的第二位置对应于第一数字信号中的第一位置，其中第二使能控制信号由 从第一使能控制信号的激活延迟。

公开(公告)号：US11563912B2

公开(公告)日：2023-01-24

申请号：US17214495

申请日：2021-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hoon Jung

IPC: H04N5/374 ,  H04N5/3745 ,  H04N5/378 ,  H01L27/146

Abstract: An image sensor includes; a sensor array generating a pixel signal, a ramp signal generator generating a ramp signal having a decreasing slope during a ramp signal enable period between a first time at which a counter enable signal is activated and a third time at which the ramp signal ends falling, a comparator comparing the pixel signal with the ramp signal to trigger an output signal, and counters, where at least one of the counters performs counting during an entire counter enable period extending between the first time and a second time at which the comparator triggers the output signal, but not all of the counters perform counting during at least one section of the counter enable period.

公开(公告)号：US10999546B2

公开(公告)日：2021-05-04

申请号：US16672692

申请日：2019-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hoon Jung

IPC: H04N5/374 ,  H04N5/3745 ,  H04N5/378 ,  H01L27/146

Abstract: An image sensor includes; a sensor array generating a pixel signal, a ramp signal generator generating a ramp signal having a decreasing slope during a ramp signal enable period between a first time at which a counter enable signal is activated and a third time at which the ramp signal ends falling, a comparator comparing the pixel signal with the ramp signal to trigger an output signal, and counters, where at least one of the counters performs counting during an entire counter enable period extending between the first time and a second time at which the comparator triggers the output signal, but not all of the counters perform counting during at least one section of the counter enable period.

公开(公告)号：US09819891B2

公开(公告)日：2017-11-14

申请号：US14989220

申请日：2016-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Soo Lee ,  Hee Sung Chae ,  Kyung Min Kim ,  Dah Som Kim ,  Sun Jung Kim ,  Seung Hoon Jung

IPC: H04N5/378 ,  H03M1/00 ,  H04N5/357

CPC classification number: H04N5/378 ,  H03M1/00 ,  H03M1/123 ,  H03M1/56 ,  H04N5/357

Abstract: The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.