公开(公告)号：US11804483B2

公开(公告)日：2023-10-31

申请号：US17177824

申请日：2021-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Ahn ,  Sung-Soo Kim ,  Chae-Ho Na ,  Dong-Hyun Roh ,  Sang-Jin Hyun

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823481

Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.

公开(公告)号：US20200098751A1

公开(公告)日：2020-03-26

申请号：US16401362

申请日：2019-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Ahn ,  Sung-Soo Kim ,  Chae-Ho Na ,  Dong-Hyun Roh ,  Sang-Jin Hyun

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.

公开(公告)号：US10950602B2

公开(公告)日：2021-03-16

申请号：US16401362

申请日：2019-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Ahn ,  Sung-Soo Kim ,  Chae-Ho Na ,  Dong-Hyun Roh ,  Sang-Jin Hyun

IPC: H01L29/76 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762

Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.

公开(公告)号：US20150347377A1

公开(公告)日：2015-12-03

申请号：US14719172

申请日：2015-05-21

Applicant: Samsung Electronics Co., Ltd

Inventor： Byoung-Jip Kim ,  Jin-Mook Lim ,  Dong-Hyun Roh ,  Kyung-Sub Min ,  Seung-Hwan Park ,  Jae-Min Park

IPC: G06F17/27 ,  G06F17/28 ,  H04L29/06

CPC classification number: G06F17/289 ,  G06F16/345 ,  G06F16/9577 ,  H04L67/2823

Abstract: A method to process contents and an electronic device thereof are provided. A method implemented by an electronic device includes transmitting contents to be summarized, attribute information of the contents, and a summarization command to a server. The method also includes receiving contents from the server that are summarized in the server based on the attribute information of the contents and the summarization command.

Abstract translation: 提供一种处理内容的方法及其电子设备。 由电子设备实现的方法包括将要汇总的内容，内容的属性信息和汇总命令发送到服务器。 该方法还包括基于内容的属性信息和汇总命令从服务器接收在服务器中总结的内容。

公开(公告)号：US20240014209A1

公开(公告)日：2024-01-11

申请号：US18473412

申请日：2023-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Ahn ,  Sung-Soo Kim ,  Chae-Ho Na ,  Dong-Hyun Roh ,  Sang-Jin Hyun

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0642 ,  H01L29/785 ,  H01L29/66545

Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.

公开(公告)号：US20210193656A1

公开(公告)日：2021-06-24

申请号：US17177824

申请日：2021-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Ahn ,  Sung-Soo Kim ,  Chae-Ho Na ,  Dong-Hyun Roh ,  Sang-Jin Hyun

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/762

Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.

公开(公告)号：US09768300B2

公开(公告)日：2017-09-19

申请号：US15406018

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

公开(公告)号：US12284827B2

公开(公告)日：2025-04-22

申请号：US18473412

申请日：2023-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Ahn ,  Sung-Soo Kim ,  Chae-Ho Na ,  Dong-Hyun Roh ,  Sang-Jin Hyun

IPC: H10D84/83 ,  H01L21/762 ,  H10D84/01 ,  H10D84/03

Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.

公开(公告)号：US10790282B2

公开(公告)日：2020-09-29

申请号：US16229207

申请日：2018-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-Jung Choi ,  Dong-Hyun Roh ,  Sung-Soo Kim ,  Gyu-Hwan Ahn ,  Sang-Jin Hyun

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/308

Abstract: A semiconductor device may include active fins spaced apart from each other by a recess therebetween, each of the active fins protruding from an upper surface of a substrate, an isolation structure including a liner on a lower surface and a sidewall of a lower portion of the recess and a blocking pattern on the liner, the blocking pattern filling a remaining portion of the lower portion of the recess and including a nitride, a carbide or polysilicon, a gate electrode structure on the active fins and the isolation structure, and a source/drain layer on a portion of each of the active fins adjacent to the gate electrode structure.

公开(公告)号：US09548301B2

公开(公告)日：2017-01-17

申请号：US15009276

申请日：2016-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成沟槽，并且沟槽可以包括有源区的切口部分。 所述方法还可以包括在沟槽中形成嵌入的应力源。 嵌入式应力器可以包括下半导体层和上半导体层，其宽度比下半导体层的宽度窄。 上半导体层的一侧可以不与下半导体层的一侧对准，并且上半导体层的最上表面可以高于有源区的最上表面。