公开(公告)号：US20150340313A1

公开(公告)日：2015-11-26

申请号：US14701777

申请日：2015-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunjung Choi ,  Kivin IM ,  Dongbok LEE ,  Inseak HWANG

IPC: H01L23/528 ,  H01L27/115 ,  H01L27/108

CPC classification number: H01L23/528 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space.

Abstract translation: 提供了包括形成在包括多个有效区域的基板上的多个非线性位线的半导体器件; 通过所述多个有效区域的多个字线; 整体间隔件，其覆盖多个非线性位线的两个侧壁并且限定暴露多个有效区域中的两个邻近区域的多个空间; 分别邻接所选择的多个空间中的一个空间中的两个相邻有效区域的两个导电图案; 以及在一个所选择的空间中形成在两个导电图案之间的接触分离绝缘层。

公开(公告)号：US20170221811A1

公开(公告)日：2017-08-03

申请号：US15491227

申请日：2017-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunjung CHOI ,  Kivin IM ,  Dongbok LEE ,  lnseak HWANG

IPC: H01L23/528 ,  H01L27/108

CPC classification number: H01L23/528 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space.