公开(公告)号：US20190244960A1

公开(公告)日：2019-08-08

申请号：US16386731

申请日：2019-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyuk PARK ,  Byoungho KWON ,  Inho KIM ,  Hyesung PARK ,  Jin-Woo BAE ,  Yanghee LEE ,  Inseak HWANG

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L22/30 ,  H01L22/34 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876

Abstract: A method of fabricating a semiconductor device includes providing a substrate including a pair of first regions and a second region therebetween, forming first patterns on the respective first regions to at least partially define a stepwise portion at the second region, and forming a dummy pattern that at least partially fills the stepwise portion. The dummy pattern may be an electrically floating structure. The dummy pattern may be formed as part of forming second patterns on the respective first regions, and the dummy pattern and the second patterns may include substantially common materials. Because the dummy pattern at least partially fills the stepwise portion at the second region, the material layer covering the second patterns and the dummy pattern may omit a corresponding stepwise portion.

公开(公告)号：US20200227419A1

公开(公告)日：2020-07-16

申请号：US16833914

申请日：2020-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyuk PARK ,  Byoungho KWON ,  Inho KIM ,  Hyesung PARK ,  Jin-Woo BAE ,  Yanghee LEE ,  Inseak HWANG

IPC: H01L27/108 ,  H01L21/66

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a semiconductor substrate including a first region and a second region, a dummy separation pattern provided on the second region of the semiconductor substrate to have a recessed region at its upper portion, a first electrode provided on the first region of the semiconductor substrate, a dielectric layer covering the first electrode, a second electrode provided on the dielectric layer, and a remaining electrode pattern provided in the recessed region. The second electrode and the remaining electrode pattern may be formed of a same material.

公开(公告)号：US20200212047A1

公开(公告)日：2020-07-02

申请号：US16814387

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyuk PARK ,  Byoungho KWON ,  Inho KIM ,  Hyesung PARK ,  Jin-Woo BAE ,  Yanghee LEE ,  Inseak HWANG

IPC: H01L27/108

Abstract: A method of fabricating a semiconductor device includes providing a substrate including a pair of first regions and a second region therebetween, forming first patterns on the respective first regions to at least partially define a stepwise portion at the second region, and forming a dummy pattern that at least partially fills the stepwise portion. The dummy pattern may be an electrically floating structure. The dummy pattern may be formed as part of forming second patterns on the respective first regions, and the dummy pattern and the second patterns may include substantially common materials. Because the dummy pattern at least partially fills the stepwise portion at the second region, the material layer covering the second patterns and the dummy pattern may omit a corresponding stepwise portion.

公开(公告)号：US20150340313A1

公开(公告)日：2015-11-26

申请号：US14701777

申请日：2015-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunjung Choi ,  Kivin IM ,  Dongbok LEE ,  Inseak HWANG

IPC: H01L23/528 ,  H01L27/115 ,  H01L27/108

CPC classification number: H01L23/528 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space.

Abstract translation: 提供了包括形成在包括多个有效区域的基板上的多个非线性位线的半导体器件; 通过所述多个有效区域的多个字线; 整体间隔件，其覆盖多个非线性位线的两个侧壁并且限定暴露多个有效区域中的两个邻近区域的多个空间; 分别邻接所选择的多个空间中的一个空间中的两个相邻有效区域的两个导电图案; 以及在一个所选择的空间中形成在两个导电图案之间的接触分离绝缘层。

公开(公告)号：US20130240959A1

公开(公告)日：2013-09-19

申请号：US13716402

申请日：2012-12-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mongsup LEE ,  Yoonho SON ,  Woogwan SHIM ,  Chan Min LEE ,  Inseak HWANG

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888

Abstract: A semiconductor device may include a substrate including an active pattern delimited by a device isolation pattern, a gate electrode crossing the active pattern, a first impurity region and a second impurity region in the active pattern on both sides of the gate electrode, a bit line crossing the gate electrode, a first contact electrically connecting the first impurity region with the bit line, and a first nitride pattern on a lower side surface of the first contact. A width of the first contact measured perpendicular to an extending direction of the bit line may be substantially equal to that of the bit line.

Abstract translation: 半导体器件可以包括：衬底，其包括由器件隔离图案限定的有源图案，与有源图案交叉的栅极电极，栅电极两侧的有源图案中的第一杂质区域和第二杂质区域，位线 跨越栅电极，将第一杂质区与位线电连接的第一接触和第一接触的下侧表面上的第一氮化物图案。 垂直于位线的延伸方向测量的第一接触件的宽度可以基本上等于位线的宽度。