公开(公告)号：US20160104763A1

公开(公告)日：2016-04-14

申请号：US14863820

申请日：2015-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunjung CHOI ,  Se Hoon OH ,  Jin-Su LEE ,  Younsoo KIM ,  HanJin LIM

IPC: H01L49/02

CPC classification number: H01L28/75 ,  H01L28/90

Abstract: A semiconductor device includes a lower electrode on a lower structure, a dielectric layer conformally covering a surface of the lower electrode, an upper electrode conformally covering a surface of the dielectric layer, and a barrier layer on the upper electrode. The barrier layer and the upper electrode define a space on a sidewall of the lower electrode.

Abstract translation: 半导体器件包括下部结构的下部电极，保形地覆盖下部电极的表面的电介质层，保持覆盖电介质层的表面的上部电极和上部电极上的阻挡层。 阻挡层和上电极在下电极的侧壁上形成空间。

公开(公告)号：US20170221811A1

公开(公告)日：2017-08-03

申请号：US15491227

申请日：2017-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunjung CHOI ,  Kivin IM ,  Dongbok LEE ,  lnseak HWANG

IPC: H01L23/528 ,  H01L27/108

CPC classification number: H01L23/528 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space.