公开(公告)号：US20190200113A1

公开(公告)日：2019-06-27

申请号：US16222902

申请日：2018-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunhye KIM ,  Norio OKADA ,  Masato SUZUKI ,  Jonghyuk CHO ,  Donghun HEO

IPC: H04R1/10

CPC classification number: H04R1/1025 ,  H02J7/0014 ,  H02J7/0021 ,  H02J7/0024 ,  H02J7/0054 ,  H02J2007/0062 ,  H04M1/6058 ,  H04M1/6066 ,  H04R2420/07 ,  H04R2420/09 ,  H04R2460/03

Abstract: An electronic device according to various embodiments of the present disclosure may include a communication interface and a processor, wherein the processor may be configured to receive first battery level information of a first earpiece and second battery level information of a second earpiece, via the communication interface, to identify a charging method corresponding to the first battery level and the second battery level, among a plurality of charging methods for charging at least one of the first earpiece or the second earpiece, and to control to supply charging power to at least one of the first earpiece or the second earpiece, via a cable which connects the electronic device with at least one of the first earpiece or the second earpiece, using the charging method.

公开(公告)号：US20230020463A1

公开(公告)日：2023-01-19

申请号：US17860699

申请日：2022-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheolhwan LIM ,  Kwangho KIM ,  Sangjin LIM ,  Haejung CHOI ,  Donghun HEO

IPC: H01L23/00 ,  G01J1/42

Abstract: A laser detecting circuit is provided. The laser detecting circuit includes a latch circuit with a first inverter configured to invert a first output signal at a first node to generate a second output signal at a second node, and a second inverter configured to generate the first output signal based on the second output signal. The second inverter includes a plurality of PMOS transistors connected in series between a first source voltage and the first node, and a plurality of NMOS transistors. A gate of each of the plurality of PMOS transistors is connected to the second node, and a drain of each of the plurality of NMOS transistors is connected to the first node. The plurality of NMOS transistors includes dummy NMOS transistors and normal NMOS transistors.