SYSTEM-ON-CHIPS AND METHODS OF CONTROLLING RESET OF SYSTEM-ON-CHIPS

    公开(公告)号:US20210232521A1

    公开(公告)日:2021-07-29

    申请号:US16929260

    申请日:2020-07-15

    Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.

    System-on-chips and methods of controlling reset of system-on-chips

    公开(公告)号:US11609874B2

    公开(公告)日:2023-03-21

    申请号:US17347769

    申请日:2021-06-15

    Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.

    System-on-chips and methods of controlling reset of system-on-chips

    公开(公告)号:US11074207B1

    公开(公告)日:2021-07-27

    申请号:US16929260

    申请日:2020-07-15

    Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.

    Connection structure for radio frequency components and electronic device including same

    公开(公告)号:US11612087B2

    公开(公告)日:2023-03-21

    申请号:US15929394

    申请日:2020-04-30

    Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present disclosure relates to connection structure for radio frequency components and electronic device including same According to various embodiments, a connection assembly for radio frequency (RF) components may include: a first RF component including an opening section and a protrusion formed in the opening section; an elastic structure; a printed circuit board (PCB); and a second RF component connected to the PCB. The elastic structure may be disposed on a first surface of the PCB, a first surface of the first RF component including the opening section may be coupled to the first surface of the PCB, and the protrusion of the first RF component may come in contact with the elastic structure, thereby forming an electrical connection between the first RF component.

    Cavity filter and antenna module including the same

    公开(公告)号:US11387564B2

    公开(公告)日:2022-07-12

    申请号:US16747887

    申请日:2020-01-21

    Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A cavity filter is provided. The cavity filter includes a plate of the cavity filter and including a feeder part for supplying an electrical signal, a housing forming an exterior of the cavity filter and coupled to the plate to form a shielded space inside the cavity filter, and a metal structure having a first end coupled to an inside of the housing and a second end that extends toward the feeder part and resonates to filter frequencies in the shielded space.

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