公开(公告)号：US20180083641A1

公开(公告)日：2018-03-22

申请号：US15650263

申请日：2017-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungho RYU ,  Dongmyung LEE ,  JaeYoul LEE ,  Kilhoon LEE ,  Jung-Pil LIM

IPC: H03L7/081 ,  H03L7/087 ,  H03L7/07 ,  H03K5/05 ,  H03K5/24 ,  G06F1/10

CPC classification number: H03L7/0814 ,  G06F1/10 ,  H03K5/05 ,  H03K5/2481 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0818 ,  H03L7/087

Abstract: A delay locked loop includes a first delay line and a second delay line. The first delay line is configured to generate a first delay clock, signal by passing an input clock, signal through a first number of logic gates among a plurality of logic gates and a second delay clock signal by passing the input clock signal through a second number of logic gates among the plurality of logic gates. The second delay line is configured to output an output clock signal based on one of a first signal having a first phase of the first delay clock signal, a second signal having a second phase of the second delay clock signal, and an interpolation signal having a third phase adjusted in stages by a reference value between the first phase and the second phase.