公开(公告)号：US20230261024A1

公开(公告)日：2023-08-17

申请号：US18306006

申请日：2023-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Kim ,  Euiyeol Kim ,  Hyounmin Baek ,  Jeong-Ho Lee ,  Youngwoo Chung ,  Heegeun Jeong

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14627 ,  H01L27/14689 ,  H01L27/14636 ,  H01L27/14603 ,  H01L27/14621

Abstract: An image sensor includes; a substrate having a first surface and an opposing second surface and including unit pixels respectively having photoelectric conversion regions, a semiconductor pattern disposed in a first trench defining the unit pixels, the semiconductor pattern including a first semiconductor layer provided on an inner surface of the first trench and a second semiconductor layer provided on the first semiconductor layer, and a first contact provided on the second surface and connected to the semiconductor pattern. A height of the first semiconductor layer from a bottom surface of the first trench is less than a height of the second semiconductor layer from the bottom surface of the first trench.

公开(公告)号：US11670661B2

公开(公告)日：2023-06-06

申请号：US16934278

申请日：2020-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung Kim ,  Euiyeol Kim ,  Hyounmin Baek ,  Jeong-Ho Lee ,  Youngwoo Chung ,  Heegeun Jeong

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14689

Abstract: An image sensor includes; a substrate having a first surface and an opposing second surface and including unit pixels respectively having photoelectric conversion regions, a semiconductor pattern disposed in a first trench defining the unit pixels, the semiconductor pattern including a first semiconductor layer provided on an inner surface of the first trench and a second semiconductor layer provided on the first semiconductor layer, and a first contact provided on the second surface and connected to the semiconductor pattern. A height of the first semiconductor layer from a bottom surface of the first trench is less than a height of the second semiconductor layer from the bottom surface of the first trench.

公开(公告)号：US11658125B2

公开(公告)日：2023-05-23

申请号：US17350878

申请日：2021-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Euiyeol Kim ,  Sun-Hyun Kim ,  Heewoo Park

IPC: H01L23/538 ,  H01L23/522 ,  H01L21/768 ,  H01L25/065 ,  H01L23/528

CPC classification number: H01L23/5386 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226 ,  H01L25/0657

Abstract: A semiconductor device may include first and second sub chips stacked sequentially and a through contact electrically connecting the first and second sub chips to each other. Each of the first and second sub chips may include a substrate and a plurality of interconnection lines, which are interposed between the substrates. The interconnection lines of the second sub chip may include first and second interconnection lines having first and second openings, respectively, which are horizontally offset from each other. The through contact may be extended from the substrate of the second sub chip toward the first sub chip and may include an auxiliary contact, which is extended toward the first sub chip through the first and second openings and has a bottom surface higher than a top surface of the uppermost one of the interconnection lines of the first sub chip.

公开(公告)号：US11049814B2

公开(公告)日：2021-06-29

申请号：US16553018

申请日：2019-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Euiyeol Kim ,  Sun-Hyun Kim ,  Heewoo Park

IPC: H01L23/538 ,  H01L23/522 ,  H01L21/768 ,  H01L25/065 ,  H01L23/528

Abstract: A semiconductor device may include first and second sub chips stacked sequentially and a through contact electrically connecting the first and second sub chips to each other. Each of the first and second sub chips may include a substrate and a plurality of interconnection lines, which are interposed between the substrates. The interconnection lines of the second sub chip may include first and second interconnection lines having first and second openings, respectively, which are horizontally offset from each other. The through contact may be extended from the substrate of the second sub chip toward the first sub chip and may include an auxiliary contact, which is extended toward the first sub chip through the first and second openings and has a bottom surface higher than a top surface of the uppermost one of the interconnection lines of the first sub chip.