公开(公告)号：US12131789B2

公开(公告)日：2024-10-29

申请号：US17847545

申请日：2022-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Kim ,  Jinyoung Kim ,  Sehwan Park ,  Seoyoung Lee ,  Jisang Lee ,  Joonsuc Jang

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: Aggressor memory cells connected to one or more aggressor wordlines are grouped into aggressor cell groups by performing a read operation with respect to the aggressor wordlines based on one or more grouping read voltages, where the aggressor wordlines are adjacent to a selected wordline corresponding to a read address among wordlines of a memory block. Selected memory cells connected to the selected wordline are grouped into a selected cell groups respectively corresponding to the aggressor cell groups. Group read conditions respectively corresponding to the selected cell groups are determined and group read operations are performed with respect to the plurality of selected cell groups based on the group read conditions. The read errors are reduced by grouping the selected memory cells into the selected cell groups according to the change of operation environments.

公开(公告)号：US20220093184A1

公开(公告)日：2022-03-24

申请号：US17324333

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisu Kim ,  Hyunggon Kim ,  Sangsoo Park ,  Joonsuc Jang ,  Minseok Kim

IPC: G11C16/26 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/24 ,  G06F11/10

Abstract: Provided is a storage device that performs a read operation by using a time interleaved sampling page buffer. The storage device controls a sensing point in time, when bit lines of even page buffer circuits are sensed, and a sensing point in time, when bit lines of odd page buffer circuits are sensed, with a certain time difference, and performs an Even Odd Sensing (EOS) operation in a stated order of even sensing and odd sensing. The storage device performs a two-step EOS operation and performs a main sensing operation on a selected memory cell according to a result of the two-step EOS operation.

公开(公告)号：US12205646B2

公开(公告)日：2025-01-21

申请号：US17483088

申请日：2021-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minseok Kim ,  Joonsuc Jang ,  Hyunggon Kim ,  Seonyong Lee

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/24 ,  G11C16/34

Abstract: A method of operating a memory device, the method including: performing a first program operation to form a plurality of first threshold voltage distributions; and performing a second program operation by using a coarse verification voltage and a fine verification voltage based on offset information to form a plurality of second threshold voltage distributions respectively corresponding to a plurality of program states from the plurality of first threshold voltage distributions, wherein the offset information includes a plurality of offsets that vary according to characteristics of the second threshold voltage distributions.

公开(公告)号：US11990189B2

公开(公告)日：2024-05-21

申请号：US17839253

申请日：2022-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghwi Yang ,  Joonsuc Jang

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings that are divided into a plurality of stacks disposed in the vertical direction, and each of the plurality of stacks includes at least one dummy word-line. The control circuit controls a program operation by applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period and by reducing a voltage level of a dummy voltage applied to the at least one dummy word-line of at least one upper stack from among the plurality of stacks during the program execution period. The at least one upper stack is disposed at a higher position than a selected stack in the vertical direction and the selected stack from among the plurality of stacks includes the selected word-line.

公开(公告)号：US11862273B2

公开(公告)日：2024-01-02

申请号：US18068337

申请日：2022-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Youngdeok Seo ,  Dongmin Shin ,  Joonsuc Jang ,  Sungmin Joe

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C16/10 ,  G11C29/12 ,  G11C16/26

CPC classification number: G11C29/42 ,  G11C16/102 ,  G11C16/26 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/4401 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1802

Abstract: A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.

公开(公告)号：US11594293B2

公开(公告)日：2023-02-28

申请号：US17336910

申请日：2021-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Garam Kim ,  Hyunggon Kim ,  Jisang Lee ,  Joonsuc Jang ,  Wontaeck Jung

IPC: G11C16/12 ,  G11C16/34 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device includes a memory cell array including a plurality of memory cells; a voltage generator configured to generate voltages used for a program operation and a verify operation for the memory cells; and control logic configured to perform a plurality of program loops while writing data to the memory cell array, such that first to N-th (e.g., N>=1) program loops including a program operation and a verify operation are performed and at least two program loops in which the verify operation is skipped are performed when a pass/fail determination of the program operation in the N-th program loop indicates a pass.

公开(公告)号：US20250053302A1

公开(公告)日：2025-02-13

申请号：US18671484

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Jisang Lee ,  Joonsuc Jang

IPC: G06F3/06

Abstract: An example memory device includes a memory cell array, a page buffer including buffer units corresponding to a plurality of memory cells of a page, a control logic configured to control a first read operation such that first hard decision data based on a normal read level and first soft decision data based on an offset level with respect to a first page are stored in the page buffer. The control logic is configured to perform a control operation of outputting the first hard decision data to a memory controller after a second read operation with respect to a second page has started in response to a first command that requests read of the second page from the memory controller and outputting the first soft decision data to the memory controller while the second read operation is being performed in response to a second command from the memory controller.

公开(公告)号：US12165721B2

公开(公告)日：2024-12-10

申请号：US18088046

申请日：2022-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangho Choi ,  Jin-Young Kim ,  Se Hwan Park ,  Il Han Park ,  Ji-Sang Lee ,  Joonsuc Jang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

公开(公告)号：US11626171B2

公开(公告)日：2023-04-11

申请号：US17201828

申请日：2021-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonsuc Jang ,  Hyunggon Kim ,  Sangbum Yun ,  Dongwook Kim ,  Kyungsoo Park ,  Sejin Baek

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C7/10 ,  G11C16/24

Abstract: A method of programming a nonvolatile memory device includes performing a single-pulse program operation in a program loop, determining whether a condition is satisfied in the a program loop, and performing a multi-pulse program operation in a next program loop when the condition is satisfied. The single-pulse program operation includes applying a first program pulse and applying plural verification pulses, the multi-pulse program operation includes applying a second program pulse, applying a third program pulse, and applying plural verification pulses, and each of the second program pulse and the third program pulse has a level lower than a level of the first program pulse.

公开(公告)号：US11574692B2

公开(公告)日：2023-02-07

申请号：US17359688

申请日：2021-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangho Choi ,  Jin-Young Kim ,  Se Hwan Park ,  Il Han Park ,  Ji-Sang Lee ,  Joonsuc Jang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.