公开(公告)号：US20220020762A1

公开(公告)日：2022-01-20

申请号：US17236053

申请日：2021-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonhwan SON ,  Gaeun KIM ,  Jeongseok LEE

IPC: H01L27/11573 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure having peripheral circuits on a semiconductor substrate, and landing pads connected to the peripheral circuits, an electrode structure on the peripheral circuit structure, the electrode structure including vertically stacked electrodes, a planarized dielectric layer that covers the electrode structure, peripheral through plugs spaced apart from the electrode structure, the peripheral through plugs penetrating the planarized dielectric layer to connect to the landing pads, conductive lines connected through contact plugs, respectively, to the peripheral through plugs, and at least one dummy through plug adjacent to a first peripheral through plug of the peripheral through plugs, the at least one dummy through plug penetrating the planarized dielectric layer and being insulated from the conductive lines.

公开(公告)号：US20230170295A1

公开(公告)日：2023-06-01

申请号：US17868899

申请日：2022-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonam KIM ,  Sejun PARK ,  Jaeduk LEE ,  Gaeun KIM

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device may include a plurality of gate electrodes apart from each other in a vertical direction on a substrate; a plurality of channel structures penetrating the plurality of gate electrodes and extending in the vertical direction; and a plurality of bit lines arranged on and connected to the plurality of channel structures. The plurality of bit lines may include a plurality of lower bit lines and a plurality of upper bit lines at different vertical levels from each other to constitute at least two layers. The plurality of upper bit lines may be apart from each other in a first horizontal direction and extend in parallel with each other in a second horizontal direction perpendicular to the first horizontal direction. A lower expansion space may be defined between two lower bit lines adjacent to each other among the plurality of lower bit lines.

公开(公告)号：US20220336298A1

公开(公告)日：2022-10-20

申请号：US17558803

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyounghoon KIM ,  Gaeun KIM ,  Joohee PARK ,  Seokwoo HONG

IPC: H01L21/66 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11556 ,  H01L23/535

Abstract: A semiconductor device and data storage system, the device including a substrate having a first region, a second region surrounding the first region, and a third region surrounding the second region; a memory structure on the first region; a first defect detector on the second region; and a dam structure on the third region, wherein the dam structure surrounds the first defect detector and includes a plurality of conductive lines stacked on the third region.