公开(公告)号：US20230170295A1

公开(公告)日：2023-06-01

申请号：US17868899

申请日：2022-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonam KIM ,  Sejun PARK ,  Jaeduk LEE ,  Gaeun KIM

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device may include a plurality of gate electrodes apart from each other in a vertical direction on a substrate; a plurality of channel structures penetrating the plurality of gate electrodes and extending in the vertical direction; and a plurality of bit lines arranged on and connected to the plurality of channel structures. The plurality of bit lines may include a plurality of lower bit lines and a plurality of upper bit lines at different vertical levels from each other to constitute at least two layers. The plurality of upper bit lines may be apart from each other in a first horizontal direction and extend in parallel with each other in a second horizontal direction perpendicular to the first horizontal direction. A lower expansion space may be defined between two lower bit lines adjacent to each other among the plurality of lower bit lines.

公开(公告)号：US20240161842A1

公开(公告)日：2024-05-16

申请号：US18338857

申请日：2023-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonam KIM ,  Sejun PARK ,  Kangin SHIN ,  Changhwan SHIN ,  Hyeji LEE ,  Woojae JANG

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/102

Abstract: Provided is a memory device with improved threshold voltage distribution and an operating method of the memory device. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate a program voltage and a verification voltage applied to the plurality of memory cells during a data write operation, and a control logic configured to control multiple program loops to program the memory cells to multiple program states during the data write operation and configured to determine whether programming passes or fails in the multiple program loops, wherein the control logic controls the program loops to verify one or more (n+1)-th memory cells to be programmed to an (n+1)-th program state by using a verify condition for verifying an n-th program state in at least one of the multiple program loops (n is an integer greater than or equal to 1).

公开(公告)号：US20230123932A1

公开(公告)日：2023-04-20

申请号：US17959365

申请日：2022-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunyeoung CHOI ,  Joonam KIM ,  Hyungjoon KIM ,  Donghwa LEE ,  Dongsung CHOI

IPC: H01L27/11556

Abstract: A method of manufacturing a semiconductor device includes forming a molded structure of stacked and alternating interlayer insulating layers and sacrificial layers on a lower structure, forming a hole through the molded structure, forming recess regions in the sacrificial layers of the molded structure, respectively, by removing a portion of the sacrificial layers, exposed through the hole, from side surfaces of the sacrificial layers, sequentially forming a preliminary blocking pattern and a charge storage pattern in each of the recess regions, sequentially forming a tunneling layer and a channel layer in the hole, forming trenches penetrating through the molded structure, such that the trenches extend in a line shape, removing the sacrificial layers exposed by the trenches, such that the preliminary blocking pattern is exposed, and oxidizing the preliminary blocking pattern, after removing the sacrificial layers, such that a blocking pattern is formed.