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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250022758A1

    公开(公告)日：2025-01-16

    申请号：US18424111

    申请日：2024-01-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yongho KIM ,  Sunoo KIM ,  Jinwoo KIM ,  Boin NOH ,  Sejun PARK ,  Jaehee OH

    IPC: H01L21/66 ,  H01L23/00

    Abstract: A semiconductor device includes a semiconductor substrate, a connection pad disposed on an interlayer insulating layer and electrically connected to an interconnection structure, a passivation layer disposed on the connection pad and having a first opening and a second opening, each exposing at least a portion of the connection pad, a first bump that includes a first lower conductive layer in contact with the connection pad within the first opening and a first upper conductive layer on the first lower conductive layer, and a second bump that includes a second lower conductive layer in contact with the connection pad within the second opening and a second upper conductive layer on the second lower conductive layer. The first and second lower conductive layers include the same material, and the first upper conductive layer and the second upper conductive layer include different materials.

    NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE
    3.
    发明公开
    NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE 审中-公开

    公开(公告)号：US20240282377A1

    公开(公告)日：2024-08-22

    申请号：US18441331

    申请日：2024-02-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chaehyeon LIM ,  Woojae JANG ,  Sejun PARK ,  Yujeong SEO ,  Jaeduk LEE

    IPC: G11C16/08 ,  G11C16/04 ,  G11C16/32

    CPC classification number: G11C16/08 ,  G11C16/0433 ,  G11C16/32

    Abstract: Provided is an operating method of a nonvolatile memory device including a plurality of cell strings, each cell string of the plurality of cell strings including a plurality of memory cells, connected between a bit line and a common source line, and vertical holes penetrating a plurality of word lines stacked in a direction perpendicular to a substrate, the operating method including applying a word line voltage to the plurality of word lines, classifying the plurality of word lines into a plurality of regions, each region of the plurality of regions including at least one of the word lines, and recovering voltages of the plurality of word lines by recovering voltages of word lines arranged in a central region among the plurality of regions before recovering voltages of word lines in other regions of the plurality of regions.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20230081402A1

    公开(公告)日：2023-03-16

    申请号：US17899832

    申请日：2022-08-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hwanyeol PARK ,  Sejun PARK ,  Junhyoung CHO ,  Sejin KYUNG ,  Daewee KONG ,  Taemin KIM

    IPC: H01L21/30

    Abstract: A method of manufacturing a semiconductor device includes preparing a substrate including cell regions and a scribe lane region, forming circuit blocks in the cell regions of the substrate, the substrate including a first surface and a second surface, forming a bias pad on the first surface of the substrate, such that the bias pad is in the scribe lane region of the substrate, bonding a deuterium exchange structure to the second surface of the substrate, implanting deuterium into the deuterium exchange structure using plasma processing, and applying a first voltage to the bias pad, such that the deuterium is diffused from the deuterium exchange structure into the substrate through the second surface of the substrate.

    MEMORY DEVICE WITH IMPROVED THRESHOLD VOLTAGE DISTRIBUTION AND OPERATING METHOD THEREOF
    5.
    发明公开
    MEMORY DEVICE WITH IMPROVED THRESHOLD VOLTAGE DISTRIBUTION AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240161842A1

    公开(公告)日：2024-05-16

    申请号：US18338857

    申请日：2023-06-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joonam KIM ,  Sejun PARK ,  Kangin SHIN ,  Changhwan SHIN ,  Hyeji LEE ,  Woojae JANG

    IPC: G11C16/34 ,  G11C16/10

    CPC classification number: G11C16/3459 ,  G11C16/102

    Abstract: Provided is a memory device with improved threshold voltage distribution and an operating method of the memory device. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate a program voltage and a verification voltage applied to the plurality of memory cells during a data write operation, and a control logic configured to control multiple program loops to program the memory cells to multiple program states during the data write operation and configured to determine whether programming passes or fails in the multiple program loops, wherein the control logic controls the program loops to verify one or more (n+1)-th memory cells to be programmed to an (n+1)-th program state by using a verify condition for verifying an n-th program state in at least one of the multiple program loops (n is an integer greater than or equal to 1).

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    7.
    发明公开
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230170295A1

    公开(公告)日：2023-06-01

    申请号：US17868899

    申请日：2022-07-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joonam KIM ,  Sejun PARK ,  Jaeduk LEE ,  Gaeun KIM

    IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

    CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A semiconductor device may include a plurality of gate electrodes apart from each other in a vertical direction on a substrate; a plurality of channel structures penetrating the plurality of gate electrodes and extending in the vertical direction; and a plurality of bit lines arranged on and connected to the plurality of channel structures. The plurality of bit lines may include a plurality of lower bit lines and a plurality of upper bit lines at different vertical levels from each other to constitute at least two layers. The plurality of upper bit lines may be apart from each other in a first horizontal direction and extend in parallel with each other in a second horizontal direction perpendicular to the first horizontal direction. A lower expansion space may be defined between two lower bit lines adjacent to each other among the plurality of lower bit lines.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20170103999A1

    公开(公告)日：2017-04-13

    申请号：US15291521

    申请日：2016-10-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Hoon LEE ,  Keejeong RHO ,  Sejun PARK ,  Jinhyun SHIN ,  Dong-Sik LEE ,  Woong-Seop LEE

    IPC: H01L27/115 ,  H01L23/528

    CPC classification number: H01L27/11582 ,  G11C16/08 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/1157

    Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.

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