公开(公告)号：US20240074149A1

公开(公告)日：2024-02-29

申请号：US18312795

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo KIM ,  Dongwook Kim ,  Sangwuk Park ,  Minkyu Suh ,  Geonyeop Lee ,  Dokeun Lee ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335

Abstract: An integrated circuit (IC) device may include a conductive area on a substrate; a first electrode connected to the conductive area on the substrate, a width of the first electrode in a lateral direction gradually increasing toward the substrate; a second electrode on the substrate, the second electrode including a silicon germanium (SiGe) film, the SiGe film surrounding the first electrode; and a dielectric film between the first electrode and the second electrode. A content of a component of the SiGe film may vary according to a distance from the substrate.

公开(公告)号：US20240147698A1

公开(公告)日：2024-05-02

申请号：US18368635

申请日：2023-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geonyeop Lee ,  Dongwook Kim ,  Yangdoo Kim ,  Sangki Nam ,  Sangwuk Park ,  Minkyu Suh ,  Dokeun Lee ,  Sungho Jang ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335

Abstract: A semiconductor device includes; a lower structure, lower electrodes on the lower structure, wherein each lower electrode includes a first lower electrode and a second lower electrode on the first lower electrode and electrically connected to the first lower electrode, an upper electrode covering the lower electrodes, and a dielectric film between the lower electrodes and the upper electrode, wherein the first lower electrode includes a pillar portion and a protruding portion on the pillar portion, wherein protruding portion has a complex shape that contacts the second lower electrode.

公开(公告)号：US20240224502A1

公开(公告)日：2024-07-04

申请号：US18527450

申请日：2023-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo Kim ,  Sangwuk Park ,  Minkyu Suh ,  Geonyeop Lee ,  Dokeun Lee ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/315

Abstract: A semiconductor memory device includes a substrate having a memory cell region and a plurality of capacitor structures in the memory cell region of the substrate, each of the plurality of capacitor structures including a lower electrode, a capacitor dielectric layer, and an upper electrode, wherein the lower electrode includes a first lower electrode, a second lower electrode above the first lower electrode, and a connecting lower electrode connecting a top end of the first lower electrode to a bottom end of the second lower electrode, wherein the upper electrode includes a bent upper electrode overlapping the connecting lower electrode in a horizontal direction, and the bent upper electrode includes a bent portion.