公开(公告)号：US20230110190A1

公开(公告)日：2023-04-13

申请号：US17938684

申请日：2022-10-07

Applicant: Samsung Electronics Co., Ltd

Inventor： JINYOUNG PARK ,  Jungpyo HONG ,  Yangdoo KIM ,  Yonghwan KIM ,  Sangwuk PARK

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/027

Abstract: Methods of forming a semiconductor device may include: providing a substrate on which a layer is formed; forming a lower hard-mask layer, which includes silicon, on the layer; forming an upper hard-mask pattern, which includes oxide, on the lower hard-mask layer; forming a lower hard-mask pattern by etching the lower hard-mask layer using the upper hard-mask pattern as an etch mask and using an etching gas that includes a metal-chloride-based first gas and a nitride-based second gas; and forming a plurality of contact holes in the layer by etching the material layer using the lower hard-mask pattern as an etch mask.

公开(公告)号：US20240074149A1

公开(公告)日：2024-02-29

申请号：US18312795

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo KIM ,  Dongwook Kim ,  Sangwuk Park ,  Minkyu Suh ,  Geonyeop Lee ,  Dokeun Lee ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335

Abstract: An integrated circuit (IC) device may include a conductive area on a substrate; a first electrode connected to the conductive area on the substrate, a width of the first electrode in a lateral direction gradually increasing toward the substrate; a second electrode on the substrate, the second electrode including a silicon germanium (SiGe) film, the SiGe film surrounding the first electrode; and a dielectric film between the first electrode and the second electrode. A content of a component of the SiGe film may vary according to a distance from the substrate.

公开(公告)号：US20230200055A1

公开(公告)日：2023-06-22

申请号：US17874691

申请日：2022-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan KIM ,  Yangdoo KIM ,  Sangwuk PARK ,  Minkyu SUH ,  Sangho LEE ,  Jungpyo HONG

IPC: H01L27/108 ,  H01L27/12 ,  H01L27/13

CPC classification number: H01L27/10817 ,  H01L27/1203 ,  H01L27/13 ,  H01L27/10852 ,  H01L27/10823

Abstract: A semiconductor device including a substrate; storage node contacts on the substrate; lower electrode structures on the storage node contacts; a supporter structure on an external side surface of the lower electrode structures and connecting adjacent lower electrode structures to each other; a dielectric layer on the lower electrode structures and the supporter structure; and an upper electrode structure on the dielectric layer, wherein the lower electrode structures each include a pillar portion in contact with the storage node contacts; and a cylinder portion on the pillar portion, the pillar portion includes a first lower electrode layer having a cylindrical shape and having a lower surface and a side surface; and a first portion covering at least an internal wall of the first lower electrode layer, and the cylinder portion includes a second portion extending from the first portion and covering an upper end of the first lower electrode layer.

公开(公告)号：US20240074163A1

公开(公告)日：2024-02-29

申请号：US18365397

申请日：2023-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo KIM ,  Sangwuk PARK ,  Minkyu SUH ,  Geonyeop LEE ,  Dokeun LEE ,  Jungpyo HONG

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/315 ,  H10B12/485

Abstract: An integrated circuit device includes a substrate having a plurality of active regions defined therein, a first word line structure including a first word line, a first gate dielectric film surrounding the first word line, and an oxide semiconductor channel layer surrounding the first gate dielectric film, the first word line structure being buried in the substrate, and crossing a first active region of the plurality of active regions, a second word line structure including a second word line and a second gate dielectric film surrounding the second word line, the second word line structure being buried in the substrate and separated from the first word line structure, and crossing the first active region, a direct contact partially passing through the first active region and the first word line structure and contacting the oxide semiconductor channel layer, and a bit line contacting the direct contact.

公开(公告)号：US20230320061A1

公开(公告)日：2023-10-05

申请号：US17979069

申请日：2022-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyu SUH ,  Yangdoo KIM ,  Yonghwan KIM ,  Sangwuk PARK ,  Geonyeop LEE ,  Dokeun LEE ,  Jungpyo HONG

IPC: H01L27/108

CPC classification number: H01L27/1085

Abstract: A method of manufacturing an integrated circuit device includes forming a mold structure, which has a mold layer and a support layer sequentially stacked, on a substrate, forming a vertical hole through the mold structure in a vertical direction and a bowing space extending outward from the vertical hole in a horizontal direction in a first vertical level area, exposing the vertical hole and the bowing space to a preprocessing atmosphere to make the support layer have a first surface state and the mold layer have a second surface state different from the first surface state, forming a bowing complementary pattern filling the bowing space by a selective deposition process using the difference between the first surface state and the second surface state, and forming a lower electrode in the vertical hole and in contact with the mold layer, the support layer, and the bowing complementary pattern.