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    Semiconductor memory device compensating difference of bitline interconnection resistance
    2.
    发明授权
    Semiconductor memory device compensating difference of bitline interconnection resistance 有权
    半导体存储器件补偿位线互连电阻的差异

    公开(公告)号：US09595315B2

    公开(公告)日：2017-03-14

    申请号：US14734315

    申请日：2015-06-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joon Han ,  Won-Kyung Park ,  Junhee Lim ,  Sungho Jang

    IPC: G11C11/4091 ,  G11C5/02 ,  G11C11/4094

    CPC classification number: G11C11/4091 ,  G11C5/02 ,  G11C11/4094 ,  G11C2207/002

    Abstract: A semiconductor memory device includes a bit line sense amplifier, a first column select gate, and a second column select gate. The bit line sense amplifier senses an electric potential difference between a bit line and a complementary bit line during a sensing operation for memory cells. The first column select gate transfers an electric potential on the bit line to a local sense amplifier based on a column select signal. The second column select gate transfers an electric potential on the complementary bit line to the local sense amplifier based on the column select signal. The first and second column select gates have different current drive abilities to compensate a difference in bit line interconnection resistance.

    Abstract translation: 半导体存储器件包括位线读出放大器，第一列选择栅极和第二列选择栅极。 在存储器单元的感测操作期间，位线读出放大器感测位线和互补位线之间的电位差。 第一列选择栅极基于列选择信号将位线上的电位传送到本地读出放大器。 第二列选择栅极基于列选择信号将互补位线上的电位传送到本地读出放大器。 第一和第二列选择栅极具有不同的电流驱动能力，以补偿位线互连电阻的差异。

    GATE STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    3.
    发明申请
    GATE STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20250040124A1

    公开(公告)日：2025-01-30

    申请号：US18442274

    申请日：2024-02-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongsik Kong ,  Sungho Jang ,  Junsoo Kim ,  Junbum Lee ,  Jaehyun Choi ,  Ilgweon Kim ,  Jeonghoon Oh

    IPC: H10B12/00

    Abstract: A gate structure includes a gate electrode on a substrate, the gate electrode including a lower portion and an upper portion sequentially stacked in a first direction substantially perpendicular to an upper surface of the substrate; a spacer structure including a second spacer and a first spacer sequentially stacked in a second direction substantially parallel to the upper surface of the substrate on a sidewall of the upper portion of the gate electrode; and a gate insulation pattern on a lower surface and a sidewall of the lower portion of the gate electrode and an outer sidewall of the spacer structure; wherein a cross-section of the first spacer has a shape of an “L”, and wherein the second spacer includes a material that is configured to induce a dipole at an interface of the first spacer and the gate insulation pattern.

    SEMICONDUCTOR DEVICE
    5.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230422479A1

    公开(公告)日：2023-12-28

    申请号：US18133964

    申请日：2023-04-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeesun Lee ,  Junsoo Kim ,  Daehyun Moon ,  Namhyun Lee ,  Seonhaeng Lee ,  Sungho Jang ,  Joohyun Jeon ,  Joon Han

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/482

    Abstract: A semiconductor device includes a first active pattern included in an upper portion of a substrate in a memory cell region, and having an isolated shape extending so that a direction oblique to a first direction is a major axis direction of the first active pattern. A first device isolation pattern provided inside a first trench included in the substrate, and covering a side wall of the first active pattern is provided. A first gate structure is provided inside a gate trench extending in the first direction on upper portions of the first active pattern and the first device isolation pattern. A barrier impurity region is selectively formed only on surfaces of both side walls of a major axis of the first active pattern. First and second impurity regions are provided on the upper portion of the first active pattern adjacent to both sides of the first gate structure.

    Integrated circuit devices
    8.
    发明授权
    Integrated circuit devices 有权

    公开(公告)号：US11437089B2

    公开(公告)日：2022-09-06

    申请号：US17245334

    申请日：2021-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taesung Kang ,  Youngkyu Lee ,  Kyoungmin Kim ,  Ilgweon Kim ,  Bokyeon Won ,  Seokjae Lee ,  Sungho Jang ,  Joon Han

    IPC: G11C11/4091 ,  H01L27/108

    Abstract: An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.

    Extreme ultraviolet exposure system
    9.
    发明授权
    Extreme ultraviolet exposure system 有权

    公开(公告)号：US11016400B1

    公开(公告)日：2021-05-25

    申请号：US16880090

    申请日：2020-05-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungho Jang ,  Sungyeol Kim ,  Hyuck Shin ,  Keunhee Bai ,  Injae Lee

    IPC: G03F7/20

    Abstract: An extreme ultraviolet exposure system includes an exposure chamber having an internal space, upper and lower electrostatic chucks, a power supply, a light source, and a mask. The upper electrostatic chuck includes first and second electrodes that are adjacent to one another and that generate an electric field of different polarities, respectively, to provide an electrostatic force. The mask is attachable to the lower surface of the upper electrostatic chuck by the electrostatic force. The mask has a metal thin film pattern including a first region in which a metal thin film that shields the electric field, and a second region in which the metal thin film is not disposed and through which the electric field is transmitted. When the mask is attached, the electric field transmitted through the second region applies an attractive force or a repulsive force to charged particles in the exposure chamber.

    Apparatus for and method of performing inspection and metrology process
    10.
    发明授权
    Apparatus for and method of performing inspection and metrology process 有权

    公开(公告)号：US10732129B2

    公开(公告)日：2020-08-04

    申请号：US16250378

    申请日：2019-01-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwang Soo Kim ,  Youngkyu Park ,  Sungho Jang ,  Byeonghwan Jeon

    IPC: G01N21/956 ,  G03F7/20

    Abstract: Disclosed are an apparatus for and a method of performing an inspection and metrology process. The apparatus may include a stage configured to load a substrate thereon, a sensor on the stage, an object lens between the sensor and the stage, a light source generating an illumination light to be transmitted to the substrate through the object lens, a first band filtering part between the light source and the object lens to control a wavelength of the illumination light within a first bandwidth, and a second band filtering part between the light source and the object lens to control a wavelength of the illumination light within a second bandwidth, which is smaller than the first bandwidth.

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