公开(公告)号：US20230223476A1

公开(公告)日：2023-07-13

申请号：US18124339

申请日：2023-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil YANG ,  Seungmin SONG ,  Geumjong BAE ,  Dong Il BAE

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/785 ,  H01L29/42356 ,  H01L29/78696 ,  H01L29/78654 ,  H01L29/78618 ,  H01L29/66772 ,  H01L29/66545 ,  H01L29/42392 ,  H01L29/41775 ,  H01L29/7845 ,  H01L29/66795 ,  H01L2029/7858 ,  H01L29/7848

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

公开(公告)号：US20220140150A1

公开(公告)日：2022-05-05

申请号：US17574166

申请日：2022-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mongsong LIANG ,  Sung-Dae SUK ,  Geumjong BAE

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L27/11 ,  H01L29/16 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

公开(公告)号：US20170170331A1

公开(公告)日：2017-06-15

申请号：US15238059

申请日：2016-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mongsong LIANG ,  Sung-Dae SUK ,  Geumjong BAE

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/78 ,  H01L29/16 ,  H01L27/11 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/78696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0673 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/78618

Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

公开(公告)号：US20240250186A1

公开(公告)日：2024-07-25

申请号：US18598672

申请日：2024-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mongsong LIANG ,  Sung-Dae SUK ,  Geumjong BAE

IPC: H01L29/786 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L29/78696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/78618 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

公开(公告)号：US20210135001A1

公开(公告)日：2021-05-06

申请号：US17140786

申请日：2021-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil YANG ,  Seungmin SONG ,  Geumjong BAE ,  Dong II BAE

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

公开(公告)号：US20200303538A1

公开(公告)日：2020-09-24

申请号：US16894270

申请日：2020-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil YANG ,  Seungmin SONG ,  Geumjong BAE ,  Dong Il BAE

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

公开(公告)号：US20170352684A1

公开(公告)日：2017-12-07

申请号：US15429719

申请日：2017-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggil YANG ,  Dong II BAE ,  Geumjong BAE ,  Seungmin SONG ,  Jongho LEE

IPC: H01L27/12 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L27/0207 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7856 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device includes an insulating layer on a substrate, a first channel pattern on the insulating layer and contacting the insulating layer, second channel patterns on the first channel pattern and being horizontally spaced apart from each other, a gate pattern on the insulating layer and surrounding the second channel patterns, and a source/drain pattern between the second channel patterns.