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公开(公告)号：US10924119B1
公开(公告)日：2021-02-16
申请号：US17000601
申请日：2020-08-24
发明人： Geumyoung Tak
摘要： A clock data recovery circuit configured to receive an input data signal that includes an embedded clock signal includes a clock recovery circuit including a phase detector configured to detect a phase of the embedded clock signal and to generate a recovery clock signal from the input data signal based on the detected phase; and a data recovery circuit configured to generate a recovery data signal from the input data signal by using the recovery clock signal. The phase detector includes a sampling latch circuit configured to output a first sample signal and a second sample signal from the input data signal; and an edge detection circuit configured to generate a phase control signal based on the first sample signal and the second sample signal and output the phase control signal in a period in which the second sample signal is output from the sampling latch circuit.
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公开(公告)号：US11233518B2
公开(公告)日：2022-01-25
申请号：US17015437
申请日：2020-09-09
发明人： Geumyoung Tak
摘要： A clock recovery circuit a first phase-locked loop (PLL) circuit configured to perform a coarse phase fixing operation on a test data signal by using a first reference clock signal, the test data signal having a prescribed pattern, and a second PLL circuit configured to perform a fine phase fixing operation on the test data signal, subsequently to the coarse phase fixing operation. The second PLL circuit may be configured to perform the fine phase fixing operation on the test data signal by selectively using at least two selection reference clock signals among a plurality of second reference clock signals that are delayed from the first reference clock signal by a unit phase, in a training mode, having a phase difference of N times the unit phase, where N is an integer equal to or greater than 2.
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