公开(公告)号：US20190333957A1

公开(公告)日：2019-10-31

申请号：US16507623

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  CHAJEA JO ,  HYOEUN KIM ,  JONGBO SHIM ,  SANG-UK HAN

IPC: H01L27/146 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.

公开(公告)号：US20200051954A1

公开(公告)日：2020-02-13

申请号：US16298476

申请日：2019-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOEUN KIM ,  JI HWANG KIM ,  JISUN YANG ,  SEUNGHOON YEON ,  CHAJEA JO ,  SANG-UK HAN

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.

公开(公告)号：US20250105127A1

公开(公告)日：2025-03-27

申请号：US18659864

申请日：2024-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dohyun KIM ,  Yeongseon KIM ,  JUHYEON KIM ,  HYOEUN KIM ,  SUNKYOUNG SEO ,  Haksun LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/544 ,  H01L25/10

Abstract: A semiconductor package may include a first dielectric structure, a first pad in the first dielectric structure, a first semiconductor chip provided on the first dielectric structure, and a bump electrically connected to the first pad. The first semiconductor chip includes: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip pad in contact with a top surface of the first pad. The first pad may be provided between the bump and the first chip of the first semiconductor chip. The first pad may include a first conductive layer and a second conductive layer covered by the first conductive layer. The bump may be positioned closer to the first conductive layer than to the second conductive layer.

公开(公告)号：US20220013501A1

公开(公告)日：2022-01-13

申请号：US17178327

申请日：2021-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： NAMHOON KIM ,  CHAJEA JO ,  Ohguk KWON ,  HYOEUN KIM ,  SEUNGHOON YEON

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

公开(公告)号：US20230215842A1

公开(公告)日：2023-07-06

申请号：US18120587

申请日：2023-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： NAMHOON KIM ,  CHAJEA JO ,  Ohguk KWON ,  HYOEUN KIM ,  SEUNGHOON YEON

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L24/02 ,  H01L2225/06513 ,  H01L2924/18161 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2224/02372 ,  H01L2225/06541

Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

公开(公告)号：US20210398929A1

公开(公告)日：2021-12-23

申请号：US17165429

申请日：2021-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOEUN KIM ,  SUNKYOUNG SEO ,  SEUNGHOON YEON ,  CHAJEA JO

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538

Abstract: A semiconductor package includes at least one second semiconductor chip stacked on a first semiconductor chip. An underfill layer is interposed between the first semiconductor chip and the at least one second semiconductor chip. The first semiconductor chip includes a first substrate, a first passivation layer disposed on the first substrate. The first passivation layer includes a first recess region. A first pad covers a bottom surface and sidewalls of the first recess region. The at least one second semiconductor chip includes a second substrate, a second passivation layer disposed adjacent to the first substrate, a conductive bump protruding outside the second passivation layer towards the first semiconductor chip and an inter-metal compound pattern disposed in direct contact with both the conductive bump and the first pad. The underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern.