公开(公告)号：US20230215842A1

公开(公告)日：2023-07-06

申请号：US18120587

申请日：2023-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： NAMHOON KIM ,  CHAJEA JO ,  Ohguk KWON ,  HYOEUN KIM ,  SEUNGHOON YEON

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L24/02 ,  H01L2225/06513 ,  H01L2924/18161 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2224/02372 ,  H01L2225/06541

Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

公开(公告)号：US20210398929A1

公开(公告)日：2021-12-23

申请号：US17165429

申请日：2021-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOEUN KIM ,  SUNKYOUNG SEO ,  SEUNGHOON YEON ,  CHAJEA JO

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538

Abstract: A semiconductor package includes at least one second semiconductor chip stacked on a first semiconductor chip. An underfill layer is interposed between the first semiconductor chip and the at least one second semiconductor chip. The first semiconductor chip includes a first substrate, a first passivation layer disposed on the first substrate. The first passivation layer includes a first recess region. A first pad covers a bottom surface and sidewalls of the first recess region. The at least one second semiconductor chip includes a second substrate, a second passivation layer disposed adjacent to the first substrate, a conductive bump protruding outside the second passivation layer towards the first semiconductor chip and an inter-metal compound pattern disposed in direct contact with both the conductive bump and the first pad. The underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern.

公开(公告)号：US20240429192A1

公开(公告)日：2024-12-26

申请号：US18401625

申请日：2023-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHAJEA JO ,  Jaejun Lee ,  Hyiyeong Jang

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a lower semiconductor chip including a first circuit layer, an upper semiconductor chip disposed on the lower semiconductor chip and including a second circuit layer, and an interconnection layer disposed between the lower semiconductor chip and the upper semiconductor chip, the interconnection layer including a plurality of pads, including at least a first pad offset from the lower semiconductor chip or the upper semiconductor chip, and a wiring portion horizontally extended and connecting the first pad of the plurality of pads to a second pad of the plurality of pads disposed between the lower semiconductor chip and the upper semiconductor chip, wherein the wiring portion of the interconnection layer electrically connects the first circuit layer to the second circuit layer.

公开(公告)号：US20200051954A1

公开(公告)日：2020-02-13

申请号：US16298476

申请日：2019-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOEUN KIM ,  JI HWANG KIM ,  JISUN YANG ,  SEUNGHOON YEON ,  CHAJEA JO ,  SANG-UK HAN

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.

公开(公告)号：US20240113057A1

公开(公告)日：2024-04-04

申请号：US18231102

申请日：2023-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUHYEON KIM ,  YEONGSEON KIM ,  SUNKYOUNG SEO ,  CHAJEA JO

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/538

CPC classification number: H01L24/08 ,  H01L23/481 ,  H01L23/5383 ,  H01L24/05 ,  H01L2224/05556 ,  H01L2224/08145

Abstract: A semiconductor package includes a first semiconductor chip stacked on a second semiconductor chip. The first semiconductor chip includes a first substrate, a first insulating layer on a lower surface of the first substrate, and a first pad exposed through the first insulating layer. The second semiconductor chip includes a second substrate, a second insulating layer on an upper surface of the second substrate contacting the first insulating layer, and a second pad exposed through the second insulating layer contacting the first pad. The first pad has an inclined side surface and a first width that increases toward the first substrate, and the second pad has an inclined side surface and a second width that increases toward the second substrate.

公开(公告)号：US20230088264A1

公开(公告)日：2023-03-23

申请号：US17839413

申请日：2022-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGCHEON PARK ,  HEONWOO KIM ,  SUNGWOO PARK ,  CHAJEA JO

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes an interposer substrate on a package substrate. The interposer substrate includes an upper pad on an upper surface of the insulating layer, a lower pad on a lower surface of the insulating layer, and a redistribution structure penetrating the insulating layer between the upper surface and the lower surface to connect the upper pad and the lower pad. A semiconductor chip is disposed above the interposer substrate and connected to the upper pad, and a connection bump directly contacts a lower surface of the lower pad. The redistribution structure includes redistribution layers and redistribution vias connected to the redistribution layers, wherein each of the redistribution layers and each of the redistribution vias includes a metal material layer and a plating seed layer, and the lower pad directly contacts the plating seed layer.

公开(公告)号：US20190333957A1

公开(公告)日：2019-10-31

申请号：US16507623

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  CHAJEA JO ,  HYOEUN KIM ,  JONGBO SHIM ,  SANG-UK HAN

IPC: H01L27/146 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.

公开(公告)号：US20210028217A1

公开(公告)日：2021-01-28

申请号：US16802683

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： YONGHOE CHO ,  CHUNGSUN LEE ,  YOONHA JUNG ,  CHAJEA JO

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/48 ,  H01L21/683

Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip.

公开(公告)号：US20180301443A1

公开(公告)日：2018-10-18

申请号：US15786698

申请日：2017-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JICHUL KIM ,  CHAJEA JO ,  SANG-UK HAN ,  KYOUNG SOON CHO ,  JAE CHOON KIM ,  WOOHYUN PARK

IPC: H01L25/18 ,  H01L27/146 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

公开(公告)号：US20160372447A1

公开(公告)日：2016-12-22

申请号：US15250951

申请日：2016-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-young JANG ,  Chang-Seong JEON ,  CHAJEA JO ,  Taeje CHO

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/1412 ,  H01L2224/1413 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17104 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/321 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83379 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode.