公开(公告)号：US20230215842A1

公开(公告)日：2023-07-06

申请号：US18120587

申请日：2023-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： NAMHOON KIM ,  CHAJEA JO ,  Ohguk KWON ,  HYOEUN KIM ,  SEUNGHOON YEON

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L24/02 ,  H01L2225/06513 ,  H01L2924/18161 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2224/02372 ,  H01L2225/06541

Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

公开(公告)号：US20230117072A1

公开(公告)日：2023-04-20

申请号：US18066487

申请日：2022-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea JO ,  Ohguk KWON ,  Namhoon KIM ,  Hyoeun KIM ,  Seunghoon YEON

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

公开(公告)号：US20210407890A1

公开(公告)日：2021-12-30

申请号：US17162418

申请日：2021-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea JO ,  Ohguk KWON ,  Namhoon KIM ,  Hyoeun KIM ,  Seunghoon YEON

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

Abstract: An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

公开(公告)号：US20240096841A1

公开(公告)日：2024-03-21

申请号：US18456261

申请日：2023-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ohguk KWON ,  Sunjae KIM ,  Seunghoon YEON ,  Seungryong OH ,  Huiyeong JANG

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065

CPC classification number: H01L24/32 ,  H01L22/32 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/3841

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of through electrodes penetrating the first substrate, and first bonding pads provided on one surface of the first substrate and electrically connected to the plurality of through electrodes, a second semiconductor chip including a second substrate, a second wiring layer provided on one surface of the second substrate and having redistribution pads and test pads, and second bonding pads on the redistribution pads, the second semiconductor chip being stacked on the first semiconductor chip via conductive bumps that are disposed between first and second bonding pads, an adhesive layer filling a space between the conductive bumps, and flow prevention structures in the adhesive layer on a test pad region where the test pads are disposed.

公开(公告)号：US20220157780A1

公开(公告)日：2022-05-19

申请号：US17375511

申请日：2021-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ohguk KWON ,  Namhoon KIM ,  Hyoeun KIM ,  Sunkyoung SEO

IPC: H01L25/065 ,  H01L23/538

Abstract: A semiconductor package including a substrate; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and at least one connection terminal between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip includes a first semiconductor chip body; and at least one upper pad on a top surface of the first semiconductor chip body and in contact with the at least one connection terminal, the at least one upper pad includes a recess that is downwardly recessed from a top surface thereof, and a depth of the recess is less than a thickness of the at least one upper pad.

公开(公告)号：US20220013501A1

公开(公告)日：2022-01-13

申请号：US17178327

申请日：2021-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： NAMHOON KIM ,  CHAJEA JO ,  Ohguk KWON ,  HYOEUN KIM ,  SEUNGHOON YEON

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.