公开(公告)号：US20250159885A1

公开(公告)日：2025-05-15

申请号：US18743326

申请日：2024-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNGYEOM KIM ,  HYUNMIN KIM ,  JUSEONG MIN ,  DONGSIK OH ,  KANGOH YUN ,  TAEKKYU YOON ,  WONHO CHANG ,  SEUNGWOOK CHOI ,  JEEHOON HAN

IPC: H10B43/27 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a first gate dielectric film on a first channel top surface of a substrate, wherein the first channel top surface is in a first region of the substrate, a first gate electrode on the first gate dielectric film, first offset insulating spacers respectively on opposing sidewalls of each of the first gate dielectric film and the first gate electrode, first main insulating spacers respectively on the opposing sidewalls of the first gate electrode, wherein the first offset insulating spacers are between the first main insulating spacers, and a pair of first source/drain regions in the substrate on opposing sides of the first gate electrode, wherein a top surface of each of the pair of first source/drain regions includes at least two first-voltage substrate step portions having respective surfaces that are lower than the first channel top surface of the substrate in a vertical direction.

公开(公告)号：US20240276729A1

公开(公告)日：2024-08-15

申请号：US18511597

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGMIN CHOI ,  HYUNMIN KIM ,  JUNTAEK PARK ,  DONGJIN LEE ,  RYOONGBIN LEE ,  JUNHEE LIM

IPC: H10B43/40 ,  H10B43/27

CPC classification number: H10B43/40 ,  H10B43/27

Abstract: A semiconductor device includes a first substrate, a transistor disposed on the first substrate, and a first interconnection layer connected to the transistor. The first interconnection layer includes a first conductive line, a second conductive line, and a third conductive line, which are spaced apart from each other in a first direction parallel to a top surface of the first substrate. The second conductive line is disposed between the first conductive line and the third conductive line. A top surface of the second conductive line is located at a height higher than top surfaces of the first and third conductive lines with respect to the top surface of the first substrate.