公开(公告)号：US20250159885A1

公开(公告)日：2025-05-15

申请号：US18743326

申请日：2024-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNGYEOM KIM ,  HYUNMIN KIM ,  JUSEONG MIN ,  DONGSIK OH ,  KANGOH YUN ,  TAEKKYU YOON ,  WONHO CHANG ,  SEUNGWOOK CHOI ,  JEEHOON HAN

IPC: H10B43/27 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a first gate dielectric film on a first channel top surface of a substrate, wherein the first channel top surface is in a first region of the substrate, a first gate electrode on the first gate dielectric film, first offset insulating spacers respectively on opposing sidewalls of each of the first gate dielectric film and the first gate electrode, first main insulating spacers respectively on the opposing sidewalls of the first gate electrode, wherein the first offset insulating spacers are between the first main insulating spacers, and a pair of first source/drain regions in the substrate on opposing sides of the first gate electrode, wherein a top surface of each of the pair of first source/drain regions includes at least two first-voltage substrate step portions having respective surfaces that are lower than the first channel top surface of the substrate in a vertical direction.

公开(公告)号：US20240324231A1

公开(公告)日：2024-09-26

申请号：US18383532

申请日：2023-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUSEONG MIN ,  JAE-BOK BAEK ,  JEEHOON HAN

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device includes: a gate electrode on a semiconductor substrate; a gate dielectric pattern between the gate electrode and the semiconductor substrate; a first semiconductor pattern on the semiconductor substrate adjacent to a first side of the gate electrode; and a second semiconductor pattern on the semiconductor substrate adjacent to a second side of the gate electrode, wherein the first semiconductor pattern includes: a first via part in contact with the semiconductor substrate; and a first plate part on the first via part, wherein the second semiconductor pattern includes: a second via part in contact with the semiconductor substrate; and a second plate part on the second via part, wherein each of the first and second plate parts extends lengthwise in a direction parallel to a top surface of the semiconductor substrate.