公开(公告)号：US20200272946A1

公开(公告)日：2020-08-27

申请号：US16650083

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-hoon KIM ,  Young-hwan PARK ,  Dong-kwan SUH ,  Keshava Prasad NAGARAJA ,  Dae-hyun KIM ,  Suk-jin KIM ,  Han-su CHO ,  Hyun-jung KIM

IPC: G06N20/10 ,  G06N3/04 ,  G06N3/08

Abstract: Disclosed is an electronic device. The An electronic device including a storage, and a processor configured to perform convolution processing on target data and kernel data based on stride information that indicates an interval at which the kernel data is applied to the target data stored in the storage, in which the processor is further configured to divide the target data into a plurality of pieces of sub-data based on first stride information, perform the convolution processing on the plurality of pieces of sub-data and a plurality of pieces of sub-kernel data respectively corresponding to the plurality of pieces of sub-data based on second stride information that is different from the first stride information, and combine a plurality of processing results, the plurality of pieces of sub-kernel data are obtained by dividing the kernel data based on the first stride information, and the second stride information indicates that the interval at which the kernel data is applied to the target data is 1.

公开(公告)号：US20190147319A1

公开(公告)日：2019-05-16

申请号：US16163772

申请日：2018-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-hoon KIM ,  Young-hwan PARK ,  Dong-kwan SUH ,  Keshava PRASAD ,  Dae-hyun KIM ,  Suk-jin KIM ,  Han-su CHO ,  Hyun-jung KIM

IPC: G06N3/04 ,  G06F17/15 ,  G06N5/04 ,  G06F12/06 ,  G06F21/52

Abstract: Provided are a method and apparatus for processing a convolution operation in a neural network. The apparatus may include a memory, and a processor configured to read, from the memory, one of divided blocks of input data stored in a memory; generate an output block by performing the convolution operation on the one of the divided blocks with a kernel; generate a feature map by using the output block, and write the feature map to the memory.

公开(公告)号：US20180276532A1

公开(公告)日：2018-09-27

申请号：US15934341

申请日：2018-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung-hoon KIM ,  Young-hwan PARK ,  Ki-seok KWON ,  Suk-jin KIM ,  Chae-seok IM ,  Han-su CHO ,  Sang-bok HAN ,  Seung-won LEE ,  Kang-jin YOON

IPC: G06N3/04 ,  G06N3/063 ,  G10L15/16 ,  G06N99/00

CPC classification number: G06N3/0454 ,  G06N3/0445 ,  G06N3/063 ,  G06N20/00 ,  G10L15/16

Abstract: An electronic apparatus for performing machine learning a method of machine learning, and a non-transitory computer-readable recording medium are provided. The electronic apparatus includes an operation module configured to include a plurality of processing elements arranged in a predetermined pattern and share data between the plurality of processing elements which are adjacent to each other to perform an operation; and a processor configured to control the operation module to perform a convolution operation by applying a filter to input data, wherein the processor controls the operation module to perform the convolution operation by inputting each of a plurality of elements configuring a two-dimensional filter to the plurality of processing elements in a predetermined order and sequentially applying the plurality of elements to the input data.

公开(公告)号：US20190311302A1

公开(公告)日：2019-10-10

申请号：US16153135

申请日：2018-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-hoon KIM ,  Young-hwan PARK ,  Dong-soo LEE ,  Dae-hyun KIM ,  Han-su CHO ,  Hyun-jung KIM

IPC: G06N99/00

Abstract: An electronic apparatus is provided. The electronic apparatus includes a first memory configured to store a first artificial intelligence (AI) model including a plurality of first elements and a processor configured to include a second memory. The second memory is configured to store a second AI model including a plurality of second elements. The processor is configured to acquire output data from input data based on the second AI model. The first AI model is trained through an AI algorithm. Each of the plurality of second elements includes at least one higher bit of a plurality of bits included in a respective one of the plurality of first elements.

公开(公告)号：US20190129885A1

公开(公告)日：2019-05-02

申请号：US16143922

申请日：2018-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-hoon KIM ,  Young-hwan PARK ,  Dong-kwan SUH ,  Keshava PRASAD NAGARAJA ,  Suk-jin KIM ,  Han-su CHO ,  Hyun-jung KIM

IPC: G06F15/80 ,  G06F9/30 ,  G06F7/544 ,  G06F15/18

Abstract: A processor for performing deep learning is provided herein. The processor includes a processing element unit including a plurality of processing elements arranged in a matrix form including a first row of processing elements and a second row of processing elements. The processing elements are fed with filter data by a first data input unit which is connected to the first row processing elements. A second data input unit feeds target data to the processing elements. A shifter composed of registers feeds instructions to the processing elements. A controller in the processor controls the processing elements, the first data input unit and second data input unit to process the filter data and target data, thus providing sum of products (convolution) functionality.