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    PROCESSOR AND METHOD OF CONTROLLING THE SAME
    1.
    发明申请
    PROCESSOR AND METHOD OF CONTROLLING THE SAME 审中-公开
    处理器及其控制方法

    公开(公告)号：US20150193375A1

    公开(公告)日：2015-07-09

    申请号：US14568400

    申请日：2014-12-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ki-seok KWON ,  Suk-jin Kim ,  Do-hyung Kim

    IPC: G06F15/76 ,  G06F9/30

    CPC classification number: G06F15/76 ,  G06F9/30145 ,  G06F9/3877 ,  G06F15/167 ,  G06F15/7867

    Abstract: A method of controlling a processor includes receiving from a command buffer a first command corresponding to a first instruction that is processed by a second processing core and starting processing of the first command by the first processing core, storing in the command buffer a second command corresponding to a second instruction that is processed by the second processing core before the processing of the first command is completed, and starting processing of a third instruction by the second processing core before the processing of the first command is completed.

    Abstract translation: 控制处理器的方法包括：从命令缓冲器接收与由第二处理核心处理的第一指令相对应的第一命令，并由第一处理核心开始处理第一命令，在命令缓冲器中存储对应于 在第一命令的处理完成之前由第二处理核心处理的第二指令，以及在完成第一命令的处理之前由第二处理核心开始第三指令的处理。

    MEMORY MANAGEMENT METHOD AND APPARATUS
    3.
    发明申请
    MEMORY MANAGEMENT METHOD AND APPARATUS 审中-公开
    内存管理方法和设备

    公开(公告)号：US20160335185A1

    公开(公告)日：2016-11-17

    申请号：US15107255

    申请日：2014-12-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-seok KWON ,  Chul-soo PARK ,  Suk-jin KIM

    IPC: G06F12/0846 ,  G06F12/0815 ,  G06F12/0886

    CPC classification number: G06F12/0851 ,  G06F12/0207 ,  G06F12/0815 ,  G06F12/0886 ,  G06F2212/621 ,  Y02D10/13

    Abstract: A memory management method includes determining a stride value for stride access by referring to a size of two-dimensional (2D) data, and allocating neighboring data in a vertical direction of the 2D data to a plurality of banks that are different from one another according to the determined stride value. Thus, the data in the vertical direction may be efficiently accessed by using a memory having a large data width.

    Abstract translation: 存储器管理方法包括通过参考二维（2D）数据的大小来确定步幅访问的步幅值，并且将2D数据的垂直方向上的相邻数据分配给彼此不同的多个存储体 到确定的步幅值。 因此，可以通过使用具有大数据宽度的存储器来有效地访问垂直方向上的数据。

    DIRECT MEMORY ACCESS CONTROLLER AND SYSTEM FOR ACCESSING CHANNEL BUFFER
    4.
    发明申请
    DIRECT MEMORY ACCESS CONTROLLER AND SYSTEM FOR ACCESSING CHANNEL BUFFER 审中-公开
    直接存储器访问控制器和用于访问通道缓冲器的系统

    公开(公告)号：US20150227479A1

    公开(公告)日：2015-08-13

    申请号：US14619783

    申请日：2015-02-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-seok KWON ,  Suk-jin KIM ,  Do-hyung KIM

    IPC: G06F13/28

    CPC classification number: G06F13/28 ,  Y02D10/14

    Abstract: A direct memory access (DMA) controller is provided. The DMA controller includes a processor interface configured to directly receive information representing a first operation sent by a processor to a buffer, and transmit data corresponding to the first operation stored in the buffer to the processor core or record data corresponding to the first operation in the buffer, and a buffer group connected to the processor interface, and including a plurality of buffers.

    Abstract translation: 提供直接存储器访问（DMA）控制器。 DMA控制器包括：处理器接口，被配置为直接接收表示由处理器发送到缓冲器的第一操作的信息，并将对应于缓冲器中存储的第一操作的数据发送到处理器核心，或者记录对应于第一操作的数据 缓冲器和连接到处理器接口的缓冲器组，并且包括多个缓冲器。

    VECTOR PROCESSOR AND CONTROL METHOD THEREFOR
    5.
    发明申请
    VECTOR PROCESSOR AND CONTROL METHOD THEREFOR 审中-公开

    公开(公告)号：US20200272478A1

    公开(公告)日：2020-08-27

    申请号：US16462086

    申请日：2017-10-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-seok KWON ,  Jae-un PARK ,  Dong-kwan SUH ,  Kang-jin YOON

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A vector processor is disclosed. The vector processor includes a plurality of register files provided to each of a plurality of single instruction multiple data (SIMD) lanes, storing each of a plurality of pieces of data, and respectively outputting input data to be used in a current cycle among the plurality of pieces of data, a shuffle unit for receiving a plurality of pieces of input data outputted from the plurality of register files, and performing shuffling such that the received plurality of pieces of input data respectively correspond to the plurality of SIMD lanes and outputting the same; and a command execution unit for performing a parallel operation by receiving input data outputted from the shuffle unit.

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