公开(公告)号：US20250105178A1

公开(公告)日：2025-03-27

申请号：US18634322

申请日：2024-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： MinKi AHN ,  Kwangho LEE ,  Heeseok LEE ,  Jaegwon JANG ,  Heejung CHOI

IPC: H01L23/00

Abstract: A semiconductor chip according to an embodiment includes a semiconductor substrate, an interconnection pad on a first surface of the semiconductor substrate, an insulation layer being on the first surface of the semiconductor substrate and defining an opening that exposes at least a partial portion of the interconnection pad, a capping pad being on the insulation layer and being connected to the interconnection pad through the opening, and an insulation structure at a periphery of the capping pad on the insulation layer.

公开(公告)号：US20230050969A1

公开(公告)日：2023-02-16

申请号：US17884143

申请日：2022-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heungkyu KWON ,  Heejung CHOI ,  Kyojin HWANG

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00

Abstract: Provided is a package-on-package (PoP). The PoP includes a lower package, an upper package on the lower package, an interposer substrate disposed between the lower package and the upper package, and a plurality of balls connecting the interposer substrate to the upper package, in which the lower package includes a first substrate, and a first die and a second die disposed side by side in a horizontal direction, on the first substrate, in which the upper package includes a second substrate, a third die on the second substrate, and a plurality of ball pads disposed on a surface of the second substrate, the interposer substrate comprises on a surface thereof a plurality of ball lands to which a plurality of balls are attached, and at least some of the plurality of ball lands overlap the first die and the second die in a vertical direction that intersects the horizontal direction.

公开(公告)号：US20220181288A1

公开(公告)日：2022-06-09

申请号：US17542667

申请日：2021-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heejung CHOI ,  Heeseok LEE ,  Junso PAK ,  Bongwee YU

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package including: a plurality of lower pads; an upper pad; a semiconductor chip including a chip pad and configured to transmit or receive a first signal through the chip pad; a first wiring structure connecting the chip pad to a first lower pad among the plurality of lower pads; and a second wiring structure connecting a second lower pad among the plurality of lower pads to the upper pad, wherein the first lower pad and the second lower pad are separated from each other by a minimum distance between the plurality of lower pads.

公开(公告)号：US20220077064A1

公开(公告)日：2022-03-10

申请号：US17307037

申请日：2021-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heejung CHOI ,  Heeseok LEE ,  Junghwa KIM

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes: a first package including a first semiconductor chip; a second package under the first package, the second package including a second semiconductor chip; and a first interposer package between the first package and the second package, the first interposer package including: a power management integrated circuit (PMIC) configured to supply power to the first package and the second package; a core member having a through-hole in which the PMIC is disposed; a first redistribution layer on the core member, and electrically connected to the first package; a second redistribution layer under the core member, and electrically connected to the second package; core vias penetrating the core member, and electrically connecting the first redistribution layer with the second redistribution layer; and a first signal path electrically connecting the first package with the second package.