公开(公告)号：US20250125998A1

公开(公告)日：2025-04-17

申请号：US18401971

申请日：2024-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsoo CHOI ,  Hiep PHAM ,  Chih-Wei YAO ,  Hyojun KIM

IPC: H04L25/02

Abstract: A wireline transceiver system includes a predriver configured to generate a signal; a source-series termination (SST) driver configured to receive the generated signal; and a replica driver configured to continuously generate bias voltages in real time to modulate current of a push-pull current source of the SST driver based on a voltage of the received signal across a process, voltage, and temperature (PVT) range.

公开(公告)号：US20200099380A1

公开(公告)日：2020-03-26

申请号：US16220898

申请日：2018-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zhiqiang HUANG ,  Chih-Wei YAO ,  Hiep PHAM

IPC: H03L7/087 ,  H03L7/10 ,  H03L7/08 ,  H04L27/227

Abstract: A synchronized in-phase/quadrature phase (I/Q) detection circuit and a method of the same are provided. The synchronized I/Q detection circuit includes a first logic circuit; a first filter; a first reset and sampling circuit; a first multiplexer; a second logic circuit; a second filter; a second reset and sampling circuit; a signal generator; and a comparator.

公开(公告)号：US20250125815A1

公开(公告)日：2025-04-17

申请号：US18409000

申请日：2024-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsoo CHOI ,  Hiep PHAM ,  Chih-Wei YAO ,  Hyojun KIM

IPC: H03M1/68

Abstract: A hybrid digital-to-analog converter (DAC) driver is provided. The hybrid DAC driver includes an upper DAC stage configured to receive an upper set of bits of a digital signal, the upper DAC stage comprising an upper set of DAC units, with a first DAC unit in the upper set of DAC units having a different weight than a second DAC unit in the upper set of DAC units; a lower DAC stage configured to receive a lower set of bits of the digital signal, the lower DAC stage comprising a lower set of DAC units formed in an R-2R resistor ladder network; and an output stage for outputting an analog signal from the upper DAC stage and the lower DAC stage.