公开(公告)号：US20240220117A1

公开(公告)日：2024-07-04

申请号：US18467959

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Jun Jin ,  Wonyoung Choi ,  Chungman Kim ,  Youngseok Lee

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0679

Abstract: A memory device according to an embodiment includes a memory cell array; a timing circuit configured to generate a first clock signal and a second clock signal, the second clock signal having a frequency that is i-times the frequency of the first clock signal; a command decoder configured to receive On-The-Fly (OTF) data including a plurality of OTF bits; a receiver configured to receive input data, configured to sample the input data based on the first clock signal, and configured to generate a first signal based on the sampled input data; a deserializer configured to generate a first deserialized signal from the first signal based on the second clock signal; a data pattern generator configured to generate a pattern signal based on the first deserialized signal and the OTF data based on the second clock signal; and a decoder configured to transmit the pattern signal to the memory cell array, where i is a natural number greater than or equal to 2.