公开(公告)号：US20230377669A1

公开(公告)日：2023-11-23

申请号：US18134776

申请日：2023-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonyoung Choi ,  Gilyoung Kang ,  Sungrae Kim ,  Hyeran Kim ,  Jeongseok Park ,  Changkyu Seol

IPC: G11C29/36 ,  G11C29/14 ,  G11C29/38

CPC classification number: G11C29/36 ,  G11C29/14 ,  G11C29/38

Abstract: A memory device, an operating method of the memory device, and a test system including the memory device. The memory device may include a decoder group configured to receive a plurality of codewords including a plurality of symbols from outside of the memory device and to decode the plurality of codewords into data patterns, a memory cell array configured to store the data patterns received from the decoder group and including a plurality of memory cells, and an encoder configured to encode the data patterns into the plurality of codewords including the plurality of symbols. The plurality of codewords may include illegal codewords and normal codewords, and the decoder group may be further configured to convert the illegal codewords among the plurality of codewords into fixed patterns, and the encoder may be configured to output the plurality of codewords to the outside of the memory device.

公开(公告)号：US20240220117A1

公开(公告)日：2024-07-04

申请号：US18467959

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Jun Jin ,  Wonyoung Choi ,  Chungman Kim ,  Youngseok Lee

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0679

Abstract: A memory device according to an embodiment includes a memory cell array; a timing circuit configured to generate a first clock signal and a second clock signal, the second clock signal having a frequency that is i-times the frequency of the first clock signal; a command decoder configured to receive On-The-Fly (OTF) data including a plurality of OTF bits; a receiver configured to receive input data, configured to sample the input data based on the first clock signal, and configured to generate a first signal based on the sampled input data; a deserializer configured to generate a first deserialized signal from the first signal based on the second clock signal; a data pattern generator configured to generate a pattern signal based on the first deserialized signal and the OTF data based on the second clock signal; and a decoder configured to transmit the pattern signal to the memory cell array, where i is a natural number greater than or equal to 2.

公开(公告)号：US12300344B2

公开(公告)日：2025-05-13

申请号：US18467959

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Jun Jin ,  Wonyoung Choi ,  Chungman Kim ,  Youngseok Lee

IPC: G11C29/56 ,  G11C29/12

Abstract: A memory device according to an embodiment includes a memory cell array; a timing circuit configured to generate a first clock signal and a second clock signal, the second clock signal having a frequency that is i-times the frequency of the first clock signal; a command decoder configured to receive On-The-Fly (OTF) data including a plurality of OTF bits; a receiver configured to receive input data, sample the input data based on the first clock signal, and generate a first signal based on the sampled input data; a deserializer configured to generate a first deserialized signal from the first signal based on the second clock signal; a data pattern generator configured to generate a pattern signal based on the first deserialized signal and the OTF data based on the second clock signal; and a decoder configured to transmit the pattern signal to the memory cell array.