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    Variable resistance memory device
    1.
    发明授权
    Variable resistance memory device 有权

    公开(公告)号：US12185647B2

    公开(公告)日：2024-12-31

    申请号：US18119970

    申请日：2023-03-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Wonjun Park ,  Chungman Kim ,  Dongho Ahn ,  Changyup Park

    IPC: G11C11/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

    Abstract: A variable resistance memory device includes a first conductive line extending on a substrate in a first horizontal direction; a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction; and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor, wherein the variable resistor includes a first variable resistance layer having a senary component represented by CaGebSbcTedAeXf, in which A and X are each a group 13 element different from each other, and 1≤a≤18, 13≤b≤26, 15≤c≤30, 35≤d≤55, 0.1≤e≤8, 0.1≤f≤8, and a+b+c+d+e+f=100.

    Resistive memory devices
    3.
    发明授权
    Resistive memory devices 有权

    公开(公告)号：US11812619B2

    公开(公告)日：2023-11-07

    申请号：US17227852

    申请日：2021-04-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinwoo Lee ,  Zhe Wu ,  Dongsung Choi ,  Chungman Kim ,  Seunggeun Yu ,  Jabin Lee ,  Soyeon Choi

    IPC: H10B63/00 ,  H10N70/00

    CPC classification number: H10B63/84 ,  H10N70/826 ,  H10N70/841

    Abstract: A resistive memory device includes a first conductive line extending in a first horizontal direction on a substrate, a plurality of second conductive lines separated from the first conductive line in a vertical direction and extending in a second horizontal direction intersecting with the first horizontal direction, on the substrate, a plurality of memory cells respectively connected between the first conductive line and one second conductive line selected from among the plurality of second conductive lines at a plurality of intersection points between the first conductive line and the plurality of second conductive lines, each of the plurality of memory cells including a selection device and a resistive memory pattern, and a bottom electrode shared by the plurality of memory cells, the bottom electrode having a variable thickness in the first horizontal direction, and including a top surface having a concave-convex shape.

    MEMORY DEVICE, MEMORY DEVICE TEST METHOD, AND TEST SYSTEM
    6.
    发明公开
    MEMORY DEVICE, MEMORY DEVICE TEST METHOD, AND TEST SYSTEM 审中-公开

    公开(公告)号：US20240220117A1

    公开(公告)日：2024-07-04

    申请号：US18467959

    申请日：2023-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hong-Jun Jin ,  Wonyoung Choi ,  Chungman Kim ,  Youngseok Lee

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0679

    Abstract: A memory device according to an embodiment includes a memory cell array; a timing circuit configured to generate a first clock signal and a second clock signal, the second clock signal having a frequency that is i-times the frequency of the first clock signal; a command decoder configured to receive On-The-Fly (OTF) data including a plurality of OTF bits; a receiver configured to receive input data, configured to sample the input data based on the first clock signal, and configured to generate a first signal based on the sampled input data; a deserializer configured to generate a first deserialized signal from the first signal based on the second clock signal; a data pattern generator configured to generate a pattern signal based on the first deserialized signal and the OTF data based on the second clock signal; and a decoder configured to transmit the pattern signal to the memory cell array, where i is a natural number greater than or equal to 2.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11581367B2

    公开(公告)日：2023-02-14

    申请号：US17209660

    申请日：2021-03-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongho Ahn ,  Segab Kwon ,  Chungman Kim ,  Kwangmin Park ,  Zhe Wu ,  Seunggeun Yu ,  Wonjun Lee ,  Jabin Lee ,  Jinwoo Lee

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.

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